Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools ◽

10.1109/dsd.2010.77 ◽

2010 ◽

Cited By ~ 13

Author(s):

Pedro Miguel Matutino ◽

Ricardo Chaves ◽

Leonel Sousa

Keyword(s):

Arithmetic Units

Developing Benchmarks for Radiation Testing of Microcontroller Arithmetic Units using ATPG

IEEE Transactions on Nuclear Science ◽

10.1109/tns.2021.3072861 ◽

2021 ◽

pp. 1-1

Author(s):

Krishna P. Gnawali ◽

Heather M. Quinn ◽

Spyros Tragoudas

Keyword(s):

Radiation Testing ◽

Arithmetic Units

Construction of subitized units is related to the construction of arithmetic units

Educational Studies in Mathematics ◽

10.1007/s10649-021-10076-7 ◽

2021 ◽

Author(s):

Jesse L. M. Wilkins ◽

Beth L. MacDonald ◽

Anderson Norton

Keyword(s):

Arithmetic Units

A CNFET full adder cell design for high-speed arithmetic units

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES ◽

10.3906/elk-1512-8 ◽

2017 ◽

Vol 25 ◽

pp. 2399-2409 ◽

Cited By ~ 3

Author(s):

Mokhtar MOHAMMADI GHANATGHESTANI ◽

Behnam GHAVAMI ◽

Honeya SALEHPOUR

Keyword(s):

High Speed ◽

Full Adder ◽

Cell Design ◽

Arithmetic Units

Base 3 vs Base 2 Synchronous Arithmetic Units

IEEE Transactions on Electronic Computers ◽

10.1109/pgec.1964.263734 ◽

1964 ◽

Vol EC-13 (5) ◽

pp. 608-609 ◽

Cited By ~ 3

Author(s):

J. Santos ◽

H. Arango

Keyword(s):

Arithmetic Units ◽

Synchronous Arithmetic

Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

Journal of Electronic Testing ◽

10.1007/bf00135230 ◽

1991 ◽

Vol 2 (4) ◽

pp. 351-372 ◽

Cited By ~ 37

Author(s):

Abhijit Chatterjee ◽

Jacob A. Abraham

Keyword(s):

Test Generation ◽

Design For Testability ◽

Graph Labeling ◽

Self Test ◽

Arithmetic Units ◽

Built In Self Test

Energy efficient spiking neural network processing using approximate arithmetic units and variable precision weights

Journal of Parallel and Distributed Computing ◽

10.1016/j.jpdc.2021.08.003 ◽

2021 ◽

Vol 158 ◽

pp. 164-175

Author(s):

Yi Wang ◽

Hao Zhang ◽

Kwang-Il Oh ◽

Jae-Jin Lee ◽

Seok-Bum Ko

Keyword(s):

Neural Network ◽

Energy Efficient ◽

Spiking Neural Network ◽

Variable Precision ◽

Arithmetic Units ◽

Network Processing

A Power Efficient System Design Methodology Employing Approximate Arithmetic Units

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2017.50 ◽

2017 ◽

Cited By ~ 1

Author(s):

Tuba Ayhan ◽

Firat Kula ◽

Mustafa Altun

Keyword(s):

System Design ◽

Design Methodology ◽

Efficient System ◽

Power Efficient ◽

Arithmetic Units

One-step high-radix signed-digit arithmetic units based on classified joint spatial encoding

Proceedings of the IEEE 1998 National Aerospace and Electronics Conference. NAECON 1998. Celebrating 50 Years (Cat. No.98CH36185) ◽

10.1109/naecon.1998.710187 ◽

2002 ◽

Author(s):

A.K. Cherri ◽

N.I. Khachab

Keyword(s):

Spatial Encoding ◽

One Step ◽

High Radix ◽

Arithmetic Units

Low-power process-variation tolerant arithmetic units using input-based elastic clocking

Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07 ◽

10.1145/1283780.1283797 ◽

2007 ◽

Cited By ~ 17

Author(s):

Debabrata Mohapatra ◽

Georgios Karakonstantis ◽

Kaushik Roy

Keyword(s):

Low Power ◽

Process Variation ◽

Arithmetic Units

Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units

Systems and Computers in Japan ◽

10.1002/1520-684x(20001115)31:12<33::aid-scj4>3.0.co;2-3 ◽

2000 ◽

Vol 31 (12) ◽

pp. 33-42

Author(s):

Yoshichika Fujioka ◽

Nobuhiro Tomabechi

Keyword(s):

Robot Control ◽

Dynamic Reconfiguration ◽

Intelligent Robot ◽

Parallel Processor ◽

Arithmetic Units