Low-power process-variation tolerant arithmetic units using input-based elastic clocking

2007 ◽  
Author(s):  
Debabrata Mohapatra ◽  
Georgios Karakonstantis ◽  
Kaushik Roy
Keyword(s):  
Low Power ◽  
Process Variation ◽  
Arithmetic Units

FinFET-Based Low Power Address Decoder under Process Variation

2016 ◽  
Author(s):  
Mukesh Chaturvedi ◽  
Akanksha Bhadoria ◽  
Vikas Mahor ◽  
Manisha Pattanaik
Keyword(s):  
Low Power ◽  
Process Variation

Low Power Reconfiguration of Approximate Arithmetic Units Using Verilog HDL

2016 ◽  
Vol 9 (9) ◽  
pp. 165-176
Author(s):  
Nithin Nagabasavanna ◽  
Nagaraju Chowdaiah
Keyword(s):  
Low Power ◽  
Verilog Hdl ◽  
Arithmetic Units

A read-disturb-free stable low power and high-density GNRFET 6T SRAM with multi-VT technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 203-214
Author(s):  
Pramod Kumar Patel ◽  
M.M. Malik ◽  
Tarun Kumar Gutpa
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Supply Voltage ◽  
Early Stage ◽  
Process Variation ◽  
High Density ◽  
Oxide Semiconductor ◽  
Mass Storage ◽  
Content Type ◽  
Sram Cell

Purpose The performance of the conventional 6T SRAM cell can be improved by using GNRFET devices with multi-threshold technology. The proposed cell shows the strong capability to operate at the minimum supply voltage of 325 mV, whereas the conventional Si-CMOS 6 T SRAM unable to operate below 725 mV, which result in an acceptable failure rate.The advance of Si-CMOS (complementary metal-oxide-semiconductor) based 6 T SRAM cell faces inherent limitation with aggressive downscaling. Hence, there is a need to propose alternatives for the conventional cells. Design/methodology/approach This study aims to improve the performance of the conventional 6T SRAM cell using dual threshold technology, device sizing, optimization of supply voltage under process variation with GNRFET technology. Further performance can be enhanced by resolving half-select issue. Findings The GNRFET-based 6T SRAM cell demonstrates that it is capable of continued improve the performance under the process, voltage, and temperature (PVT) variations significantly better than its CMOS counterpart. Research limitations/implications Nano-material fabrication technology of GNRFETs is in the early stage; hence, the different transistor models can be used to evaluate the parameters of future GNRFETs circuit. Practical implications GNRFET devices are suitable for implementing low power and high density SRAM cell. Social implications The conventional Si-CMOS 6 T SRAM cell is a core component and used as the mass storage element in cache memory in computer system organization, mobile phone and other data storage devices. Originality/value This paper presents a new approach to implement an alternative design of GNRFET -based 6T SRAM cell with doped reservoirs that also supports process variation. In addition, multi-threshold technology optimizes the performance of the proposed cell. The proposed design provides a means to analyze delay and power of GNRFET-based SRAM under process variation with considering edge roughness, and offers design and fabrication insights for cell in the future.

Process variation aware dual-Vth assignment technique for low power nanoscale CMOS design

2011 ◽  
Vol 51 (12) ◽  
pp. 2357-2365 ◽  
Author(s):  
Sudhakar S. Mande ◽  
Saurabh A. Chandorkar ◽  
A.N. Chandorkar
Keyword(s):  
Low Power ◽  
Process Variation ◽  
Nanoscale Cmos ◽  
Cmos Design
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