A Power Efficient System Design Methodology Employing Approximate Arithmetic Units

2017 ◽  
Author(s):  
Tuba Ayhan ◽  
Firat Kula ◽  
Mustafa Altun
Keyword(s):  
System Design ◽  
Design Methodology ◽  
Efficient System ◽  
Power Efficient ◽  
Arithmetic Units

Power-efficient System Design

2010 ◽  
Author(s):  
Preeti Ranjan Panda ◽  
B. V. N. Silpa ◽  
Aviral Shrivastava ◽  
Krishnaiah Gummidipudi
Keyword(s):  
System Design ◽  
Efficient System ◽  
Power Efficient

scholarly journals Power-Efficient System Design for Cellular-Based Machine-to-Machine Communications

2013 ◽  
Vol 12 (11) ◽  
pp. 5740-5753 ◽  
Author(s):  
Harpreet S. Dhillon ◽  
Howard C. Huang ◽  
Harish Viswanathan ◽  
Reinaldo A. Valenzuela
Keyword(s):  
System Design ◽  
Efficient System ◽  
Machine To Machine ◽  
Power Efficient

Road Sign System Design for Aging Population

2013 ◽  
Vol 869-870 ◽  
pp. 247-250
Author(s):  
Wen Li Lu ◽  
Ming Wei Liu
Keyword(s):  
Older People ◽  
System Design ◽  
Experimental Method ◽  
The Elderly ◽  
Efficient System ◽  
The Road ◽  
Road Signs ◽  
Road Sign ◽  
Sign System ◽  
Board System

With the growth with the citys population of elderly people, the symptoms of aging are becoming more and more significant. Older people are faced with complex circumstances when they are outdoors, a correct and efficient system of road signs should help them reach their destinations safely. Therefore, a well designed system for the elderly is vital. The following research is concentrated on the design of the road sign system focusing upon the aspects of placement positions, height of the text and symbols, and the amount of information included on the sign. This will assist in the design of the most useful and efficient sign board system for the elderly. This will be determined through the experimental method.

scholarly journals Design of Power Efficient 32-Bit Processing Unit

2018 ◽  
Vol 7 (2.16) ◽  
pp. 52
Author(s):  
Dharmavaram Asha Devi ◽  
Chintala Sandeep ◽  
Sai Sugun L
Keyword(s):  
Low Power ◽  
System Design ◽  
Power Analysis ◽  
Low Power Design ◽  
Design Flow ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Front End ◽  
Verification Process

The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.  

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