Voltage gain-controlled third-generation current conveyor and its all-pass filter verification

This article given a second generation current controlled current conveyor positive (CCCII+), second generation current controlled current conveyor negative (CCCII-), Quadrature oscillator with high-Q frequency choosing network and implementing completely different phase oscillators by employing (CCCII+) positive and (CCCII-) negative, and high band pass filter network, the approach is predicted on the CMOS technology . The root of this concept is, considering a customary voltage mode oscillator which consists of band pass filter with prime quality issue (high-Q) and voltage mode amplifier is transfigure into current mode oscillator by replacing tans-conductance amplifier. Because the loop of the oscillator is has lavish selectivity, the oscillator process less distortion. In addition 3dB bandwidth, oscillating condition, oscillation frequency of the oscillator could linearly, independently and electronically be tuned by adjusting the bias current of the (CCCII±)[1], lastly different simulations have been carried out to verify the linearity between output and input ports, range of frequency operations. These results can justify that the designed circuits are workable.

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High-Linearity Direct Conversion Receiver with the Transconductance Equalization Technique and DCOC Method

Electronics ◽

10.3390/electronics10161966 ◽

2021 ◽

Vol 10 (16) ◽

pp. 1966

Author(s):

Yiming Han ◽

Fengjie Wang ◽

Jiarui Liu ◽

Zhiyu Wang ◽

Faxin Yu

Keyword(s):

Direct Conversion ◽

Low Noise ◽

Low Noise Amplifier ◽

Voltage Gain ◽

Pass Filter ◽

Low Pass Filter ◽

Direct Conversion Receivers ◽

High Linearity ◽

Equalization Technique ◽

Noise Amplifier

To improve the linearity of direct conversion receivers (DCRs), two high-linearity methods for high second-order intercept points (IP2s) and high third-order intercept points (IP3s) are proposed. To improve IP3s, a transconductance equalization technique for a complementary input operational amplifier (OPAMP) is proposed in an active-RC low-pass filter (LPF), while a digital-analog hybrid DC offset calibration (DCOC) method is proposed to improve IP2s. For one thing, the proposed transconductance equalization technique employs a pair of resistors to guarantee high voltage gain for an OPAMP with two-stage Miller topology under a high-input voltage swing to improve linearity with little deterioration of the noise performance. For another, during the DCOC method, the low-noise amplifier is turned off and replaced by an equivalent resistance of the output impedance of the low-noise amplifier to ensure the accuracy and effectiveness of the DCOC method. Fabricated in 40-nm CMOS technology, the receiver with proposed methods can realize a noise figure of 2.6–3.5 dB in the full frequency band, with an OIP3 of 28 dBm, an IM2 more than 70 dBc, and a remaining DC of −53.2 dBm under the total voltage gain of 60 dB.

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