Preeminent Buffer Insertion Technique For Long Advanced On-Chip Graphene Interconnects

2018 ◽  
Author(s):  
Takshashila Pathade ◽  
Urmi Shah ◽  
Yash Agrawal ◽  
Rutu Parekh
Keyword(s):  
Buffer Insertion ◽  
Insertion Technique ◽  
On Chip

scholarly journals On-chip interconnects modeling and timing driven buffer insertion

2021 ◽  
Author(s):  
Alaa R. Abdullah
Keyword(s):  
Closed Form ◽  
Performance Modeling ◽  
Vlsi Design ◽  
Electrical Circuit ◽  
Equivalent Electrical Circuit ◽  
Buffer Insertion ◽  
Insertion Technique ◽  
Rc Circuit ◽  
On Chip ◽  
Transition Times

With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well known methods that are used to map an interconnect to an equivalent electrical circuit. In this thesis, a general approach that considers z-parameters is developed witch allows the generation of equivalent RC, RLC, and RLCG circuits for both T and ∏ configurations. The performance of these generated circuits is compared to H-spice simulations by measuring the effect of interconnects on the transition times and delays under different conditions such as input transition times, interconnect lengths and capacitive loads. As a result, the a-configuration of AWE method reveals consistently an acceptable performance which makes it a good candidate to be utilized for buffer insertion.Buffer insertion is a popular technique used to reduce the delay of a long interconnect by segmenting it and inserting buffers among these segments. Therefore, the performance of this technique depends strongly on the accuracy of the considered interconnect model. However, using a model such as the RLCG of ∏ configuration which is derived from using the AWE method is not practical due to the complexity accompanied by such model which makes the derivation of closed-form expressions very complicated. To overcome this dilemma, the selected configuration has been mapped to a simple equivalent RC circuit. As a consequence, a new RC representation of on-chip interconnects is developed. Moreover, depending on the developed RC model, the proposed buffer insertion technique shows superiority over previously published works.

scholarly journals On-chip interconnects modeling and timing driven buffer insertion

2021 ◽  
Author(s):  
Alaa R. Abdullah
Keyword(s):  
Closed Form ◽  
Performance Modeling ◽  
Vlsi Design ◽  
Electrical Circuit ◽  
Equivalent Electrical Circuit ◽  
Buffer Insertion ◽  
Insertion Technique ◽  
Rc Circuit ◽  
On Chip ◽  
Transition Times

With the increasing effect of on-chip interconnects on nowadays [sic] VLSI design performance, modeling of interconnects becomes a necessity. GAM, TPN, and AWE are well known methods that are used to map an interconnect to an equivalent electrical circuit. In this thesis, a general approach that considers z-parameters is developed witch allows the generation of equivalent RC, RLC, and RLCG circuits for both T and ∏ configurations. The performance of these generated circuits is compared to H-spice simulations by measuring the effect of interconnects on the transition times and delays under different conditions such as input transition times, interconnect lengths and capacitive loads. As a result, the a-configuration of AWE method reveals consistently an acceptable performance which makes it a good candidate to be utilized for buffer insertion.Buffer insertion is a popular technique used to reduce the delay of a long interconnect by segmenting it and inserting buffers among these segments. Therefore, the performance of this technique depends strongly on the accuracy of the considered interconnect model. However, using a model such as the RLCG of ∏ configuration which is derived from using the AWE method is not practical due to the complexity accompanied by such model which makes the derivation of closed-form expressions very complicated. To overcome this dilemma, the selected configuration has been mapped to a simple equivalent RC circuit. As a consequence, a new RC representation of on-chip interconnects is developed. Moreover, depending on the developed RC model, the proposed buffer insertion technique shows superiority over previously published works.

scholarly journals Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip

2005 ◽  
Author(s):  
S.S. Kallakuri ◽  
A. Doboli ◽  
E.A. Feinberg
Keyword(s):  
System Of Systems ◽  
Buffer Insertion ◽  
Systems On Chip ◽  
Buffer Sizing ◽  
On Chip

A signal integrity-driven buffer insertion technique for post-routing noise and delay optimization

2003 ◽  
Author(s):  
K. Chakraborty ◽  
D.E. Long ◽  
J.P. Fishburn ◽  
K. Singhal ◽  
Lun Ye ◽  
...  
Keyword(s):  
Signal Integrity ◽  
Buffer Insertion ◽  
Insertion Technique ◽  
Delay Optimization

An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

2020 ◽  
pp. 2150065
Author(s):  
Muhammad Mazher Iqbal ◽  
Husain Parvez ◽  
Fasahat Hussain ◽  
Muhammad Rashid
Keyword(s):  
Boolean Functions ◽  
Reconfigurable Architecture ◽  
External Memory ◽  
Memory Cells ◽  
Insertion Technique ◽  
Dynamically Reconfigurable ◽  
On Chip ◽  
Tailored Design ◽  
Application Specific ◽  
Logic Blocks

An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, different dynamically reconfigurable application circuits are initially mapped and tested on an FPGA fabric. Subsequently, the FPGA fabric is reduced to achieve an efficient architecture for known application circuits. However, a large portion of ASIF is still occupied by fully flexible logic blocks, containing the same amount of area and SRAM memory cells, as found in a traditional FPGA. Thus, here lies a potential to further optimize the logic blocks of an ASIF at the expense of removing or reducing their reconfigurability. This work optimizes the logic blocks of an ASIF through the SRAM-Table sharing technique, without compromising their reconfigurability. Moreover, the routing channels of ASIF are further optimized by applying the Boolean functions (Gates) insertion technique. The applied techniques (SRAM-Table sharing and Boolean functions insertion) not only reduce the area, delay and power, but also minimize the reconfiguration time, bitstream size and the size of external memory required to store the bitstream of circuits. This optimized version of ASIF is termed as ASIF[Formula: see text]. Furthermore, an embedded FPGA in a System-on-Chip that requires the partial dynamic reconfiguration for known circuits, can be automatically reduced to an ASIF[Formula: see text]. It is found through experimental results that an ASIF[Formula: see text] is 4–9[Formula: see text] area-efficient and requires [Formula: see text] lesser number of SRAM cells, as compared to the previously proposed ASIF for a group of 2–5 circuits. It also achieves 34–53[Formula: see text] area saving as compared to a traditional FPGA.

Gut microbiome a promising target for management of respiratory diseases

2020 ◽  
Vol 477 (14) ◽  
pp. 2679-2696
Author(s):  
Riddhi Trivedi ◽  
Kalyani Barve
Keyword(s):  
Respiratory Diseases ◽  
New Technology ◽  
Bacterial Flora ◽  
Systemic Circulation ◽  
The Body ◽  
Lung Pathology ◽  
Promising Target ◽  
Current Therapies ◽  
Intestinal Microbial Flora ◽  
On Chip

The intestinal microbial flora has risen to be one of the important etiological factors in the development of diseases like colorectal cancer, obesity, diabetes, inflammatory bowel disease, anxiety and Parkinson's. The emergence of the association between bacterial flora and lungs led to the discovery of the gut–lung axis. Dysbiosis of several species of colonic bacteria such as Firmicutes and Bacteroidetes and transfer of these bacteria from gut to lungs via lymphatic and systemic circulation are associated with several respiratory diseases such as lung cancer, asthma, tuberculosis, cystic fibrosis, etc. Current therapies for dysbiosis include use of probiotics, prebiotics and synbiotics to restore the balance between various species of beneficial bacteria. Various approaches like nanotechnology and microencapsulation have been explored to increase the permeability and viability of probiotics in the body. The need of the day is comprehensive study of mechanisms behind dysbiosis, translocation of microbiota from gut to lung through various channels and new technology for evaluating treatment to correct this dysbiosis which in turn can be used to manage various respiratory diseases. Microfluidics and organ on chip model are emerging technologies that can satisfy these needs. This review gives an overview of colonic commensals in lung pathology and novel systems that help in alleviating symptoms of lung diseases. We have also hypothesized new models to help in understanding bacterial pathways involved in the gut–lung axis as well as act as a futuristic approach in finding treatment of respiratory diseases caused by dysbiosis.

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