Contamination assessment of inductive couple plasma etching chamber under mixture of recipes using statistical method

2011 ◽  
Author(s):  
Cher Ming Tan ◽  
Minh Due Le
Keyword(s):  
Statistical Method ◽  
Plasma Etching ◽  
Contamination Assessment ◽  
Couple Plasma ◽  
Inductive Couple Plasma

Optimization of time on CF4/O2 etchant for inductive couple plasma reactive ion etching of TiO2 thin film

2016 ◽  
Author(s):  
R. Adzhri ◽  
M. K. Md. Arshad ◽  
M. F. M. Fathil ◽  
U. Hashim ◽  
A. R. Ruslinda ◽  
...  
Keyword(s):  
Thin Film ◽  
Tio2 Thin Film ◽  
Reactive Ion Etching ◽  
Ion Etching ◽  
Couple Plasma ◽  
Inductive Couple Plasma

Inductive couple plasma reactive ion etching characteristics of TiO2 thin films

2015 ◽  
Vol 587 ◽  
pp. 20-27 ◽  
Author(s):  
Adrian Adalberto Garay ◽  
Su Min Hwang ◽  
Chee Won Chung
Keyword(s):  
Thin Films ◽  
Reactive Ion Etching ◽  
Tio2 Thin Films ◽  
Ion Etching ◽  
Couple Plasma ◽  
Inductive Couple Plasma

Using the secondary electrons (SE) of SEM with NIST‘s MONSEL-II program to obtain improved linewidth measurements and slope angles of line edges on a MMIC GaAs device

1996 ◽  
Vol 54 ◽  
pp. 944-945
Author(s):  
Richard G. Sartore
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Microwave Integrated Circuits ◽  
Monolithic Microwave Integrated Circuits ◽  
Thick Gold ◽  
Gaas Devices ◽  
Source Distance ◽  
Margin Of Error ◽  
Dimensional Measurements ◽  
Barrier Metal

In the evaluation of GaAs devices from the MMIC (Monolithic Microwave Integrated Circuits) program for Army applications, there was a requirement to obtain accurate linewidth measurements on the nominal 0.5 micrometer gate lengths used to fabricate these devices. Preliminary measurements indicated a significant variation (typically 10 % to 30% but could be more) in the critical dimensional measurements of the gate length, gate to source distance and gate to drain distance. Passivation introduced a margin of error, which was removed by plasma etching. Additionally, the high aspect ratio (4-5) of the thick gold (Au) conductors also introduced measurement difficulties. The final measurements were performed after the thick gold conductor was removed and only the barrier metal remained, which was approximately 250 nanometer thick platinum on GaAs substrate. The thickness was measured using the penetration voltage method. Linescan of the secondary electron signal as it scans across the gate is shown in Figure 1.

Silicon layers grown over SiO2 by liquid phase epitaxy: Electron Microscopical study

1990 ◽  
Vol 48 (4) ◽  
pp. 566-567
Author(s):  
F. Banhart ◽  
F.O. Phillipp ◽  
R. Bergmann ◽  
E. Czech ◽  
M. Konuma ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Liquid Phase ◽  
Plasma Etching ◽  
Liquid Phase Epitaxy ◽  
Three Dimensional ◽  
Microscopical Study ◽  
Sample Temperature ◽  
Structural Defects ◽  
Si Substrates ◽  
Etched Surface

Defect-free silicon layers grown on insulators (SOI) are an essential component for future three-dimensional integration of semiconductor devices. Liquid phase epitaxy (LPE) has proved to be a powerful technique to grow high quality SOI structures for devices and for basic physical research. Electron microscopy is indispensable for the development of the growth technique and reveals many interesting structural properties of these materials. Transmission and scanning electron microscopy can be applied to study growth mechanisms, structural defects, and the morphology of Si and SOI layers grown from metallic solutions of various compositions.The treatment of the Si substrates prior to the epitaxial growth described here is wet chemical etching and plasma etching with NF3 ions. At a sample temperature of 20°C the ion etched surface appeared rough (Fig. 1). Plasma etching at a sample temperature of −125°C, however, yields smooth and clean Si surfaces, and, in addition, high anisotropy (small side etching) and selectivity (low etch rate of SiO2) as shown in Fig. 2.

Sign in / Sign up

Export Citation Format

Share Document