An Approach for Optimizing Yield of Embedded Memories on Mobile SoC Chips

Author(s):  
V. Simhadri ◽  
N. Agrawal ◽  
B. Talatam ◽  
H. Kim ◽  
T. Schink ◽  
...  
Keyword(s):  
Author(s):  
Pascal Meinerzhagen ◽  
Adam Teman ◽  
Robert Giterman ◽  
Noa Edri ◽  
Andreas Burg ◽  
...  
Keyword(s):  

Author(s):  
Chuang Cheng ◽  
Chih-Tsun Huang ◽  
Jing-Reng Huang ◽  
Cheng-Wen Wu ◽  
Chen-Jong Wey ◽  
...  
Keyword(s):  

Nanomaterials ◽  
2021 ◽  
Vol 11 (9) ◽  
pp. 2382
Author(s):  
Omar Abou El Kheir ◽  
Marco Bernasconi

Chalcogenide GeSbTe (GST) alloys are exploited as phase change materials in a variety of applications ranging from electronic non-volatile memories to neuromorphic and photonic devices. In most applications, the prototypical Ge2Sb2Te5 compound along the GeTe-Sb2Te3 pseudobinary line is used. Ge-rich GST alloys, off the pseudobinary tie-line with a crystallization temperature higher than that of Ge2Sb2Te5, are currently explored for embedded phase-change memories of interest for automotive applications. During crystallization, Ge-rich GST alloys undergo a phase separation into pure Ge and less Ge-rich alloys. The detailed mechanisms underlying this transformation are, however, largely unknown. In this work, we performed high-throughput calculations based on Density Functional Theory (DFT) to uncover the most favorable decomposition pathways of Ge-rich GST alloys. The knowledge of the DFT formation energy of all GST alloys in the central part of the Ge-Sb-Te ternary phase diagram allowed us to identify the cubic crystalline phases that are more likely to form during the crystallization of a generic GST alloy. This scheme is exemplified by drawing a decomposition map for alloys on the Ge-Ge1Sb2Te4 tie-line. A map of decomposition propensity is also constructed, which suggests a possible strategy to minimize phase separation by still keeping a high crystallization temperature.


Author(s):  
Hanlin Xie ◽  
Zhihong Liu ◽  
Wenrui Hu ◽  
Yu Gao ◽  
Hui Teng Tan ◽  
...  

Abstract AlN/GaN metal-insulator-semiconductor high electron mobility transistors (MISHEMTs) on silicon substrate using in-situ SiN as gate dielectric were fabricated and their RF power performance at mobile system-on-chip (SoC) compatible voltages was measured. At a mobile SoC-compatible supply voltage of Vd = 3.5 V/5 V, the 90-nm gate-length AlN/GaN MISHEMTs showed a maximum power-added efficiency (PAE) of 62%/58%, a maximum output power density (Poutmax) of 0.44 W/mm/0.84 W/mm and a linear gain of 20 dB/19 dB at the frequency of 5 GHz. These results suggest that the in-situ-SiN/AlN/GaN-on-Si MISHEMTs are promising for RF power amplifiers in 5G mobile SoC applications.


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