Comparative study of WL driving method for high-capacity NAND flash memory

2016 ◽  
Author(s):  
Junyoung Ko ◽  
Younghwi Yang ◽  
Seong-ook Jung ◽  
Jisu Kim ◽  
Cheon An Lee ◽  
...  
Keyword(s):  
Comparative Study ◽  
Flash Memory ◽  
High Capacity ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals Machine Learning-Based Optimization Technique for High-Capacity V-NAND Flash Memory

2021 ◽  
Author(s):  
Jisuk Kim ◽  
Earl Kim ◽  
Daehyeon Lee ◽  
Taeheon Lee ◽  
Daesik Ham ◽  
...  
Keyword(s):  
Machine Learning ◽  
Genetic Algorithm ◽  
Flash Memory ◽  
State Of The Art ◽  
Optimization Technique ◽  
High Capacity ◽  
Turnaround Time ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
The Individual

Abstract In the NAND flash manufacturing process, thousands of internal electronic fuses (eFuse) should be tuned in order to optimize performance and validity. In this paper, we propose a machine learning-based optimization technique that can automatically tune the individual eFuse value based on a deep learning and genetic algorithm. Using state-of-the-art triple-level cell (TLC) V-NAND flash wafers, we trained our model and validated its effectiveness. The experimental results show that our technique can automatically optimize NAND flash memory, thus reducing total turnaround time (TAT) by 70 % compared with the manual-based process.

Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory

2019 ◽  
Vol 27 (8) ◽  
pp. 1828-1839
Author(s):  
Junyoung Ko ◽  
Younghwi Yang ◽  
Jisu Kim ◽  
Cheonan Lee ◽  
Young-Sun Min ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Capacity ◽  
Nand Flash ◽  
Nand Flash Memory

A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage

2021 ◽  
pp. 1-1
Author(s):  
Daehoon Na ◽  
Jang-woo Lee ◽  
Seon-Kyoo Lee ◽  
Hwasuk Cho ◽  
Junha Lee ◽  
...  
Keyword(s):  
Flash Memory ◽  
High Performance ◽  
High Capacity ◽  
Nand Flash ◽  
Nand Flash Memory

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

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