EOS/ESD protection circuit design for deep submicron SOI technology

Electrical Overstress/Electrostatic Discharge Symposium Proceedings ◽

10.1109/eosesd.1995.478287 ◽

1995 ◽

Author(s):

S. Ramaswamy ◽

P. Raha ◽

E. Rosenbaum ◽

Sung-Mo Kang

Keyword(s):

Circuit Design ◽

Deep Submicron ◽

Esd Protection ◽

Protection Circuit ◽

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An ESD protection circuit for SOI technology using gate- and body-biased MOSFETs

IEEE International SOI Conference SOI-02 ◽

10.1109/soi.2002.1044410 ◽

2002 ◽

Author(s):

Salman ◽

Mitra ◽

Ioannou ◽

Fechner ◽

Liu

Keyword(s):

Esd Protection ◽

Protection Circuit ◽

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Layout and Technology Influences on ESD Protection Circuit Design

On-Chip ESD Protection for Integrated Circuits - The International Series in Engineering and Computer Science ◽

10.1007/0-306-47618-5_7 ◽

2006 ◽

pp. 171-218

Keyword(s):

Circuit Design ◽

Esd Protection ◽

Protection Circuit

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Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes

Proceedings of International Electron Devices Meeting ◽

10.1109/iedm.1995.499280 ◽

2002 ◽

Author(s):

A. Amerasekera ◽

C. Duvvury ◽

V. Reddy ◽

M. Rodder

Keyword(s):

Circuit Design ◽

Deep Submicron ◽

Protection Circuit ◽

Submicron Cmos ◽

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Function-based ESD protection circuit design verification for BGA pad-ring array

2015 IEEE 11th International Conference on ASIC (ASICON) ◽

10.1109/asicon.2015.7516902 ◽

2015 ◽

Author(s):

Li Wang ◽

Rui Ma ◽

Fei Lu ◽

Albert Wang ◽

Zongyu Dong ◽

...

Keyword(s):

Circuit Design ◽

Design Verification ◽

Esd Protection ◽

Protection Circuit

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Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) ◽

10.1109/aspdac.2004.1337685 ◽

2005 ◽

Author(s):

R.Y. Zhan ◽

H.G. Feng ◽

Q. Wu ◽

X.K. Guan ◽

G. Chen ◽

...

Keyword(s):

Circuit Design ◽

Extraction Method ◽

Critical Parameters ◽

Design Verification ◽

Esd Protection ◽

Protection Circuit

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Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/92.532032 ◽

1996 ◽

Vol 4 (3) ◽

pp. 307-321 ◽

Author(s):

Ming-Dou Ker ◽

Chung-Yu Wu ◽

Tao Cheng ◽

Hun-Hsien Chang

Keyword(s):

Low Voltage ◽

Deep Submicron ◽

Esd Protection ◽

Protection Circuit

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A novel ESD protection circuit for ultra-deep-submicron low power mixed-signal IC designs

2007 7th International Conference on ASIC ◽

10.1109/icasic.2007.4415648 ◽

2007 ◽

Author(s):

Ta-Lee Yu ◽

Li-Hsien Fan ◽

Huijuan Cheng ◽

Jing Liu ◽

Xianmin Chen ◽

...

Keyword(s):

Low Power ◽

Deep Submicron ◽

Mixed Signal ◽

Esd Protection ◽

Protection Circuit ◽

Mixed Signal Ic

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Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

Microelectronics Reliability ◽

10.1016/j.microrel.2007.07.095 ◽

2007 ◽

Vol 47 (9-11) ◽

pp. 1502-1505 ◽

Author(s):

Shih-Hung Chen ◽

Ming-Dou Ker

Keyword(s):

Integrated Circuits ◽

Circuit Design ◽

Cmos Integrated Circuits ◽

Device Model ◽

Charged Device Model ◽

Esd Protection ◽

Protection Circuit ◽

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Input ESD protection circuit design with special considerations for gate oxide protection in nanoscale technologies

2014 IEEE International Conference on Electron Devices and Solid-State Circuits ◽

10.1109/edssc.2014.7061125 ◽

2014 ◽

Author(s):

Guangyi Lu ◽

Yuan Wang ◽

Jian Cao ◽

Song Jia ◽

Ganggang Zhang ◽

...

Keyword(s):

Circuit Design ◽

Esd Protection ◽

Protection Circuit

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A Novel RC-Triggered Bidirectional ESD Protection Circuit in SOI Technology

2019 8th International Symposium on Next Generation Electronics (ISNE) ◽

10.1109/isne.2019.8896534 ◽

2019 ◽

Author(s):

Yan Wang ◽

Zhiwei Liu ◽

Jizhi Liu

Keyword(s):

Esd Protection ◽

Protection Circuit ◽

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