A galvanic isolated evaluation of a NTC thermistor using a logarithmic amplifier

We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR achieved in this work is a result of cascading three amplification stages to construct the LPGA in addition to the lower common-mode gain of the proposed logarithmic amplification topology. In addition, the 1 / f noise and the inherent DC offset voltage of the input transistors are reduced using a chopper stabilization technique. The CMOS 180 nm standard technology is used to implement the circuits. Experimental results for the integrated LPGA show a CMRR of 140 dB, a differential gain of 37 dB, an input-referred noise of 0.754 μ Vrms, a 189 μ W power consumption from 1.8 V power supply and occupies an active area of 0.4 mm 2 .

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Sintering-modified oxymanganospinel ceramics for NTC thermistor application

2012 IEEE International Conference on Oxide Materials for Electronic Engineering (OMEE) ◽

10.1109/omee.2012.6464846 ◽

2012 ◽

Author(s):

I. Hadzaman ◽

H. Klym ◽

O. Shpotyuk ◽

M. Brunner ◽

V. Balitska

Keyword(s):

Ntc Thermistor

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A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

Journal of Circuits System and Computers ◽

10.1142/s0218126618501049 ◽

2018 ◽

Vol 27 (07) ◽

pp. 1850104 ◽

Cited By ~ 2

Author(s):

Yuwadee Sundarasaradula ◽

Apinunt Thanachayanont

Keyword(s):

Low Power ◽

Biomedical Applications ◽

Dynamic Range ◽

Supply Voltage ◽

Low Noise ◽

Power Supply Voltage ◽

Wide Dynamic Range ◽

Dc Offset ◽

Limiting Amplifier ◽

Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

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