A Linear Time Partitioning Algorithm for Frequency Weighted Impurity Functions

2020 ◽  
Author(s):  
Thuan Nguyen ◽  
Thinh Nguyen
Keyword(s):  
Linear Time ◽  
Time Partitioning ◽  
Partitioning Algorithm

scholarly journals A Contraction-based Ratio-cut Partitioning Algorithm

VLSI Design ◽  
2002 ◽  
Vol 15 (2) ◽  
pp. 485-489
Author(s):  
Youssef Saab
Keyword(s):  
Linear Time ◽  
Fundamental Problem ◽  
Cluster Formation ◽  
Vlsi Circuits ◽  
Iterative Improvement ◽  
Partitioning Algorithm ◽  
Partitioning Algorithms ◽  
Simple Ratio ◽  
Iterative Partitioning

Partitioning is a fundamental problem in the design of VLSI circuits. In recent years, ratio-cut partitioning has received attention due to its tendency to partition circuits into their natural clusters. Node contraction has also been shown to enhance the performance of iterative partitioning algorithms. This paper describes a new simple ratio-cut partitioning algorithm using node contraction. This new algorithm combines iterative improvement with progressive cluster formation. Under suitably mild assumptions, the new algorithm runs in linear time. It is also shown that the new algorithm compares favorably with previous approaches.

scholarly journals A Timing-Driven Partitioning System for Multiple FPGAs

VLSI Design ◽  
1996 ◽  
Vol 4 (4) ◽  
pp. 309-328
Author(s):  
Kalapi Roy ◽  
Carl Sechen
Keyword(s):  
Simulated Annealing ◽  
Performance Optimization ◽  
Clustering Algorithm ◽  
Linear Time ◽  
Critical Path ◽  
Path Delay ◽  
Timing Model ◽  
Longest Path ◽  
Partitioning Algorithm ◽  
Circuit Components

Field-programmable systems with multiple FPGAs on a PCB or an MCM are being used by system designers when a single FPGA is not sufficient. We address the problem of partitioning a large technology mapped FPGA circuit onto multiple FPGA devices of a specific target technology. The physical characteristics of the multiple FPGA system (MFS) pose additional constraints to the circuit partitioning algorithms: the capacity of each FPGA, the timing constraints, the number of I/Os per FPGA, and the pre-designed interconnection patterns of each FPGA and the package. Existing partitioning techniques which minimize just the cut sizes of partitions fail to satisfy the above challenges. We therefore present a timing driven N-way partitioning algorithm based on simulated annealing for technology-mapped FPGA circuits. The signal path delays are estimated during partitioning using a timing model specific to a multiple FPGA architecture. The model combines all possible delay factors in a system with multiple FPGA chips of a target technology. Furthermore, we have incorporated a new dynamic net-weighting scheme to minimize the number of pin-outs for each chip. Finally, we have developed a graph-based global router for pin assignment which can handle the pre-routed connections of our MFS structure. In order to reduce the time spent in the simulated annealing phase of the partitioner, clusters of circuit components are identified by a new linear-time bottom-up clustering algorithm. The annealing-based N-way partitioner executes four times faster using the clusters as opposed to a flat netlist with improved partitioning results. For several industrial circuits, our approach outperforms the recursive min-cut bi-partitioning algorithm by 35% in terms of nets cut. Our approach also outperforms an industrial FPGA partitioner by 73% on average in terms of unroutable nets. Using the performance optimization capabilities in our approach we have successfully partitioned the MCNC benchmarks satisfying the critical path constraints and achieving a significant reduction in the longest path delay. An average reduction of 17% in the longest path delay was achieved at the cost of 5% in total wire length.

scholarly journals A New 2-way Multi-level Partitioning Algorithm

VLSI Design ◽  
2000 ◽  
Vol 11 (3) ◽  
pp. 301-310 ◽  
Author(s):  
Youssef Saab
Keyword(s):  
State Of The Art ◽  
Linear Time ◽  
Fundamental Problem ◽  
Vlsi Circuits ◽  
Iterative Improvement ◽  
Multi Level ◽  
Partitioning Algorithm ◽  
Partitioning Algorithms

Partitioning is a fundamental problem in the design of VLSI circuits. In recent years, the multi-level partitioning approach has been used with success by a number of researchers. This paper describes a new multi-level partitioning algorithm (PART) that combines a blend of iterative improvement and clustering, biasing of node gains, and local uphill climbs. PART is competitive with recent state-of-the-art partitioning algorithms. PART was able to find new lower cuts for many benchmark circuits. Under suitably mild assumptions, PART also runs in linear time.

A Real Time Control Architecture for Continuously Managing Patients in a Care Unit

1995 ◽  
Vol 34 (05) ◽  
pp. 475-488
Author(s):  
B. Seroussi ◽  
J. F. Boisvieux ◽  
V. Morice
Keyword(s):  
Real Time ◽  
Linear Time ◽  
Treatment Plan ◽  
Control Architecture ◽  
Real Time Control ◽  
Time Representation ◽  
Time Control ◽  
Continuous Support ◽  
Definition Of ◽  
Computerized System

Abstract:The monitoring and treatment of patients in a care unit is a complex task in which even the most experienced clinicians can make errors. A hemato-oncology department in which patients undergo chemotherapy asked for a computerized system able to provide intelligent and continuous support in this task. One issue in building such a system is the definition of a control architecture able to manage, in real time, a treatment plan containing prescriptions and protocols in which temporal constraints are expressed in various ways, that is, which supervises the treatment, including controlling the timely execution of prescriptions and suggesting modifications to the plan according to the patient’s evolving condition. The system to solve these issues, called SEPIA, has to manage the dynamic, processes involved in patient care. Its role is to generate, in real time, commands for the patient’s care (execution of tests, administration of drugs) from a plan, and to monitor the patient’s state so that it may propose actions updating the plan. The necessity of an explicit time representation is shown. We propose using a linear time structure towards the past, with precise and absolute dates, open towards the future, and with imprecise and relative dates. Temporal relative scales are introduced to facilitate knowledge representation and access.

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