scholarly journals Multi-level sequential circuit partitioning for test vector generation for low power test in VLSI

2011 ◽  
Vol 2 (11) ◽  
Author(s):  
VH Prathyush ◽  
K Somasundaram
Keyword(s):  
Low Power ◽  
Test Vector ◽  
Circuit Partitioning ◽  
Sequential Circuit ◽  
Power Test ◽  
Low Power Test ◽  
Vector Generation ◽  
Multi Level ◽  
Test Vector Generation

Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon’s Low-Complexity Chase

2020 ◽  
Vol 67 (12) ◽  
pp. 3362-3366
Author(s):  
Francisco Garcia-Herrero ◽  
Alfonso Sanchez-Macian ◽  
Juan Antonio Maestro
Keyword(s):  
Low Power ◽  
Low Complexity ◽  
Low Latency ◽  
Test Vector ◽  
Power Test ◽  
Low Power Test

Access-in-turn test architecture for low-power test application

2016 ◽  
Vol 104 (3) ◽  
pp. 433-441 ◽  
Author(s):  
Weizheng Wang ◽  
JinCheng Wang ◽  
Zengyun Wang ◽  
Lingyun Xiang
Keyword(s):  
Low Power ◽  
Power Test ◽  
Low Power Test ◽  
Test Application ◽  
Test Architecture
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