Abstract
This paper presents an analysis of Reversible Switching Capacitive Digital to Analog converter (RSC-DAC) based low power Successive Approximation Register Analog to Digital Converter (SAR-ADC).The proposed structure involves, the QVDC (Quantum Voltage Differential Comparator) constructed using Simple Transconductance Amplifier (STA) technique , the RSC-DAC switching energy reduced by 93% contrast to the standard Charge Redistribution Switching Capacitive DAC (CRSC-DAC) method, and the Successive Approximation Register(SAR) control logic is designed with D-FF based shift register. The QVDC comparator allows very small voltage comparison, and consumes low power and area effective. The linearity parameters such as Integral Nonlinearity, Differential Nonlinearity and parasitic effect of the capacitor of the RSC-DAC is analyzed and improved by the new approach is named as Adaptive Random Code Generation (ARCG) Technique. The above overall design is implemented by TANNER-EDA tool in 250nm CMOS technology, consumes 1.74mW power at 60MS/s. The INL and DNL of the proposed structure is +0.18/-0.12 LSB and +0.11/-0.05 LSB respectively.
Ultra‐low‐voltage low‐power dynamic comparator with forward body bias scheme for SAR ADC