Analysis of Reversible Switching Capacitive DAC Based Low Power SAR-ADC

Code Generation ◽

Low Voltage ◽

Signal To Noise Ratio ◽

Sar Adc ◽

Control Logic ◽

Digital To Analog Converter ◽

Differential Nonlinearity ◽

Offset Voltage

This paper presents an analysis of the Reduced Switching Capacitor Digital-to-Analog Converter (RSC-DAC)-based low power Successive Approximation Register Analog to Digital Converter (SAR-ADC). The proposed structure involves the Low voltage Static D-Latch Comparator (LSD-LC) with pre-amplifier operators in two modes (Normal and Hold), the RSC-DAC switching energy, reduced by 93% contrast to the standard Charge Redistribution Switching Capacitor DAC (CRSC-DAC) method, and the Successive Approximation Register (SAR) control logic. The LSD-LC with pre-amplifier consists of a latch circuit and a pre-amplifier. The pre-amplifier is often used to eliminate the DC offset voltage and kickback noise without substantially weakening the Signal-to-Noise Ratio (SNR) to drive the main circuit while the latch is needed for comparison. The linearity parameters such as Integral Nonlinearity, Differential Nonlinearity and effect of parasitic capacitances of the RSC-DAC are analyzed and improved by the new approach named as Adaptive Random Code Generation (ARCG) Technique. The above overall design is implemented in 250-nm CMOS design of the TANNER-EDA tool, consuming 1.74-mW power at 60[Formula: see text]MS/s. The proposed structure has an INL and a DNL, respectively, of +0.18/[Formula: see text] LSB and +0.11/[Formula: see text]0.05 LSB.

Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC

Journal of Circuits System and Computers ◽

10.1142/s0218126617500773 ◽

2017 ◽

Vol 26 (05) ◽

pp. 1750077 ◽

Cited By ~ 1

Author(s):

Anush Bekal ◽

Shabi Tabassum ◽

Manish Goswami

Keyword(s):

Low Power ◽

Digital Control ◽

Low Power Design ◽

Cmos Technology ◽

Control Logic ◽

Control Block ◽

Logic Block ◽

External Clock ◽

Asynchronous Sar

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

Journal of Circuits System and Computers ◽

10.1142/s0218126614500236 ◽

2014 ◽

Vol 23 (02) ◽

pp. 1450023

Author(s):

MOHAMED O. SHAKER ◽

MAGDY A. BAYOUMI

Keyword(s):

Power Consumption ◽

Low Power ◽

Power Supply ◽

Cmos Technology ◽

Clock Signal ◽

Switching Activity ◽

Simulation Results ◽

Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

10.32920/ryerson.14652180.v1 ◽

2021 ◽

Author(s):

Daniel Junehee Lee

Keyword(s):

Power Consumption ◽

Cmos Technology ◽

Sar Adc ◽

Least Significant Bit ◽

Silicon Area ◽

Analog To Digital ◽

Power Efficient ◽

Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

A Low Power Dynamic Comparator For A 12-Bit Pipelined Successive Approximation Register (SAR) ADC

2018 4th International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcsyst.2018.8605130 ◽

2018 ◽

Cited By ~ 2

Author(s):

D. S. Shylu ◽

S. Jasmine ◽

D. Jackuline Moni

Keyword(s):

Low Power ◽

Sar Adc ◽

Dynamic Comparator ◽

Power Dynamic ◽

Successive Approximation Register

A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

10.32920/ryerson.14652180 ◽

2021 ◽

Author(s):

Daniel Junehee Lee

Keyword(s):

Power Consumption ◽

Cmos Technology ◽

Sar Adc ◽

Least Significant Bit ◽

Silicon Area ◽

Analog To Digital ◽

Power Efficient ◽

Simulation Results

file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

Implementation of 32-BIT Pipelined ADC Using 90nm Analog CMOS Technology

International Journal for Research in Applied Science and Engineering Technology ◽

10.22214/ijraset.2021.37002 ◽

2021 ◽

Vol 9 (VII) ◽

pp. 3073-3080

Author(s):

Sarita Chauhan

Keyword(s):

Low Power ◽

Cmos Technology ◽

High Energy ◽

Sar Adc ◽

Analog To Digital Converter ◽

Digital Converter ◽

Analog To Digital ◽

Successive Approximation Adc ◽

Analog Cmos

After seeing the technological evolution, we have understood about the A/D converter that it is the meeting point of the analog to digital domains. As technology is being continuously scaled down, the transistor sizes have decreased drastically resulting in reduced area and power consumption in the digital domain. The successive approximation ADC is best suitable for low power applications with moderate speed and simple design. Here, the implementation of 32-bit pipelined analog-to-digital converter with the help of successive approximation register based Sub-ADC. The SAR ADC architectures are popular for achieving high energy efficiency and low power applications. But they suffer from resolution and speed limitation. To overcome the speed limitations of SAR ADC, we proposed the implementation of 90nm using CMOS technology of a low power, high speed pipelined analog-to-digital converter (ADC). The capacitive digital-to-analog converter (DAC), two stage CMOS comparator with output inverter of proposed ADC are lower than those of a conventional ADC. To achieve low power and to minimize the size of the input sampling capacitance in order to ease durability.