On-chip area-efficient spectrum analyzer for testing analog IC

Author(s):  
M.A. Dominguez ◽  
J.L. Ausin ◽  
G. Torelli ◽  
J.F. Duque-Carillo
Author(s):  
A Suresh ◽  
Sreehari Rao Patri ◽  
Debasish Dwibedy ◽  
Sunilkumar Bhat ◽  
K Gaurav ◽  
...  

2006 ◽  
Vol 22 (4-6) ◽  
pp. 437-448 ◽  
Author(s):  
M. A. Domínguez ◽  
J. L. Ausín ◽  
J. F. Duque-Carrillo ◽  
G. Torelli

Author(s):  
Wen Huang ◽  
Moyang Li ◽  
Songbin Gong ◽  
Xiuling Li

Two types of on-chip RFIC transformers based on CMOS compatible strain-induced self-rolled-up membrane (S-RuM) nanotechnology, with extremely small footprint, are demonstrated. The rolled-up transformers, with their 3D tubular form factors, dramatically reduce the substrate parasitic effects and push the maximum working frequency into millimeter wave bands with a coupling coefficient, k, as high as 0.92. The 3D stand-up nature also allows the tube transformers to be less susceptible to residue stress in the substrate and thus compatible with flexible platforms for wearable RF applications. The demonstrated samples with a turn ratio, n, of 5.5:1 only occupies 805 μm2 on-chip area (s) which is 12x smaller than that of the best planar transformer with the same turn ratio, and its figure of merit n·k/s, is therefore ∼ 6046/mm2, enhanced by 15x.


2020 ◽  
Vol 143 (2) ◽  
Author(s):  
Yaser Hadad ◽  
Vahideh Radmard ◽  
Srikanth Rangarajan ◽  
Mahdi Farahikia ◽  
Gamal Refai-Ahmed ◽  
...  

Abstract The industry shift to multicore microprocessor architecture will likely cause higher temperature nonuniformity on chip surfaces, exacerbating the problem of chip reliability and lifespan. While advanced cooling technologies like two phase embedded cooling exist, the technological risks of such solutions make conventional cooling technologies more desirable. One such solution is remote cooling with heatsinks with sequential conduction resistance from chip to module. The objective of this work is to numerically demonstrate a novel concept to remotely cool chips with hotspots and maximize chip temperature uniformity using an optimized flow distribution under constrained geometric parameters for the heatsink. The optimally distributed flow conditions presented here are intended to maximize the heat transfer from a nonuniform chip power map by actively directing flow to a hotspot region. The hotspot-targeted parallel microchannel liquid cooling design is evaluated against a baseline uniform flow conventional liquid cooling design for the industry pressure drop limit of approximately 20 kPa. For an average steady-state heat flux of 145 W/cm2 on core areas (hotspots) and 18 W/cm2 on the remaining chip area (background), the chip temperature uniformity is improved by 10%. Moreover, the heatsink design has improved chip temperature uniformity without a need for any additional system level complexity, which also reduces reliability risks.


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