Construction of the cyclic block-type LDPC codes for low complexity hardware implementation

2008 ◽  
Author(s):  
Kuang-Hao Lin ◽  
Robert C. Chang ◽  
Chien-Lin Huang ◽  
Sheng-Dong Wu
Keyword(s):  
Hardware Implementation ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Block Type ◽  
Cyclic Block

A BP Decoding Algorithm Based on Nodes Residual for LDPC Codes and its Hardware Implementation

2011 ◽  
Vol 128-129 ◽  
pp. 7-10
Author(s):  
Zhong Xun Wang ◽  
Xing Cheng Wang ◽  
Fang Qiang Zhu
Keyword(s):  
Hardware Implementation ◽  
Belief Propagation ◽  
Dynamic Scheduling ◽  
Ldpc Codes ◽  
Ldpc Code ◽  
Low Complexity ◽  
Decoding Algorithm ◽  
Fast Decoding ◽  
Good For

We researched BP decoding algorithm based on variable-to-check information residual for LDPC code (VC-RBP) in this paper. It is a dynamic scheduling belief propagation using residuals, and has some advantages，such as fast decoding, good performance, and low complexity. It is similar to residual belief propagation (RBP),but has some difference in computing the residual message. This paper further optimized the new algorithm on DSP of TMS320dm6446, and it is good for hardware implementation.

A Min-Sum Algorithm Suitable for Hardware Implementation Based on LDPC Codes

2011 ◽  
Vol 271-273 ◽  
pp. 458-463
Author(s):  
Rui Ping Chen ◽  
Zhong Xun Wang ◽  
Xin Qiao Yu
Keyword(s):  
Hardware Implementation ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Scaling Factor ◽  
Computation Complexity ◽  
Decoding Complexity ◽  
Decoding Algorithms ◽  
Hardware Resource ◽  
Simulation Results ◽  
Ber Performance

Decoding algorithms with strong practical value not only have good decoding performance, but also have the computation complexity as low as possible. For this purpose, the paper points out the modified min-sum decoding algorithm(M-MSA). On the condition of no increasing in the decoding complexity, it makes the error-correcting performance improved by adding the appropriate scaling factor based on the min-sum algorithm(MSA), and it is very suitable for hardware implementation. Simulation results show that this algorithm has good BER performance, low complexity and low hardware resource utilization, and it would be well applied in the future.

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

scholarly journals Design and efficient hardware implementation schemes for non-Quasi-Cyclic LDPC codes

2017 ◽  
Vol 22 (01) ◽  
pp. 92-103
Author(s):  
Baihong Lin ◽  
Yukui Pei ◽  
Liuguo Yin ◽  
Jianhua Lu
Keyword(s):  
Hardware Implementation ◽  
Ldpc Codes

Low-complexity high-rate irregular QC-LDPC codes with applications to PR2 and EPR2 channels

2012 ◽  
Vol 25 (3) ◽  
pp. 370-382
Author(s):  
Virasit Imtawil ◽  
Mongkol Kupimai ◽  
Anan Kruesubthaworn ◽  
Apirat Siritaratiwat ◽  
Anupap Meesomboon
Keyword(s):  
Ldpc Codes ◽  
Low Complexity ◽  
High Rate

A Low-Complexity EMS Algorithm with Dynamic Message Truncation for Non-Binary LDPC Codes

2021 ◽  
Author(s):  
Fulong Wang ◽  
Ming Zhan ◽  
Qian Zhang ◽  
Hao Tang ◽  
Yunkai Feng ◽  
...  
Keyword(s):  
Ldpc Codes ◽  
Low Complexity

Auto White Balance Algorithm in Digital Camera

2012 ◽  
Vol 182-183 ◽  
pp. 2080-2084
Author(s):  
Jie Li ◽  
Xue Xiang Wang ◽  
Hao Liu
Keyword(s):  
Hardware Implementation ◽  
Digital Camera ◽  
Low Complexity ◽  
Light Sources ◽  
Light Conditions ◽  
Threshold Method ◽  
White Balance ◽  
White Point ◽  
A New Technique ◽  
Better Than

Auto white balance (AWB) is an important function of digital camera. The purpose of white balance is to adjust the image to make it look like taken under standard light conditions. We present a new technique to detect the reference white point of image in this paper. This technique detects the white point of image by using dynamic threshold method, thus making it more flexible and more applicable compared to other algorithms. We test 50 images which were taken under different light sources, and find that this algorithm is better than or comparable to other algorithms both in subjective and objective aspects. At the same time, this algorithm has low complexity, and it can be easily applied to hardware implementation.

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