Low Voltage, Low Power, High Linearity, High Speed CMOS Voltage Mode Analog Multiplier

2009 ◽  
Author(s):  
B. C. Akshatha ◽  
Vijay Kumar Akshintala
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Analog Multiplier ◽  
Voltage Mode ◽  
High Linearity

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

A low voltage CMOS analog multiplier with high linearity

2009 ◽  
Author(s):  
Amir H. Miremadi ◽  
Ahmad Ayatollahi ◽  
Adib Abrishamifar ◽  
Alireza Siadatan
Keyword(s):  
Low Voltage ◽  
Analog Multiplier ◽  
High Linearity
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