scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

scholarly journals A 0.3 V, Rail-to-Rail, Ultralow-Power, Non-Tailed, Body-Driven, Sub-Threshold Amplifier

2021 ◽  
Vol 11 (6) ◽  
pp. 2528 ◽  
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Gain Bandwidth ◽  
Common Mode ◽  
Input Stage ◽  
Fully Differential ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
Ultralow Power

A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is proposed in this paper. The input stage exploits a replica bias control loop to set the common mode current and a common mode feed-forward strategy to set its output common mode voltage. This novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered operational amplifier. A dual path compensation strategy is exploited to improve the frequency response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around 3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of 60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and mismatch variations.

LOW VOLTAGE LOW POWER FULLY DIFFERENTIAL BUFFER

2009 ◽  
Vol 18 (03) ◽  
pp. 497-502 ◽  
Author(s):  
VINCENZO STORNELLI
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Common Mode ◽  
Figures Of Merit ◽  
Fully Differential ◽  
General Performance ◽  
Rail To Rail ◽  
The Common

In this paper a useful CMOS fully-differential buffer topology is presented. The proposed solution, performing the common mode feedback operation, shows a rail-to-rail characteristic, so it is particularly suitable for low-voltage (± 0.75 V) low-power (< 400 μW) applications. The simulated results have shown excellent general performance, evaluated in terms of suitable figures of merit.

scholarly journals A 4-μW 0.8-V Rail-to-Rail Input/Output CMOS Fully Differential OpAmp

1970 ◽  
pp. 22
Author(s):  
M.R. Valero ◽  
S. Celma ◽  
N. Medrano
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Cmos Technology ◽  
Open Loop ◽  
Threshold Region ◽  
Input Output ◽  
Output Stage ◽  
Common Mode ◽  
Ultra Low Power ◽  
Rail To Rail

This paper presents an ultra low power rail-to-rail input/output operational amplifier (OpAmp) designed in a low cost 0.18 μm CMOS technology. In this OpAmp, rail-to-rail input operation is enabled by using complementary input pairs with gm control. To maximize the output swing a rail-to-rail output stage is employed. For low-voltage low-power operation, the operating transistors in the input and output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, and the slew-rate is 0.04 V/μs with a 10 pF capacitive load connected to each of the amplifier outputs. For the same load, the simulated unity gain frequency is 131 kHz with a 64º phase margin. A common-mode feed-forward circuit (CMFF) increases CMRR, reducing drastically the variations in the output common mode voltage and keeping the DC gain almost constant. In fact, their relative error remains below 1.2 % for a (-20ºC, +120ºC) temperature span. In addition, the proposed OpAmp is very simple and consumes only 4 μW at 0.8 V supply.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

2015 ◽  
Vol 19 ◽  
pp. 19-36 ◽  
Author(s):  
P.A. Gowri Sankar ◽  
G. Sathiyabama
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
Field Effect ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Flash Adc ◽  
Simulation Results

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

scholarly journals Design of High Speed and Precision and Low-Power LVDS Driver for CMOS Image Sensor

2020 ◽  
Vol 38 (2) ◽  
pp. 442-450
Author(s):  
Chuangze Li ◽  
Benguang Han ◽  
Jie He ◽  
Longsheng Wu
Keyword(s):  
Low Power ◽  
High Frequency ◽  
High Speed ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Compensation Method ◽  
Common Mode ◽  
General Design ◽  
Frequency Components ◽  
The Common

Aiming at the requirement of high speed and precision, low-power and large-capacity load of serial data interface for aerospace super large array(15k×15k) CMOS image sensor, a design scheme low voltage differential signal (LVDS) driver by combining the split-length method with the pre-emphasis technique is proposed. Firstly, comparing with the general design schemes, the present scheme uses the split-length compensation method to increase effectively the unity-gain bandwidth while keeping the op-amp gain constant. Secondly, the pre-emphasis technique is used to compensate the LVDS driver for high-frequency components to improve the driving capability of the capacitive load and high speed signal integrity (SI). The simulation results show that the accuracy of the common-mode feedback voltage is improved by using the split-length compensation method, and also the common-mode voltage changes below 15 mV. The pre-emphasis technique is used to enhance the amplitude of the high-frequency components lost during the high-speed transmission. The quality of the signal eye diagram during high-speed transmission reduces the bit error rate, and both the transmission rate and the driving load capacity are two times more than the general design (1.2 Gb/s@12 pF), and the quiescent current consumption is only 4.6 mA@12 pF. The present LVDS driver design is implemented in a typical CMOS process of 0.18 μm.

An Ultra Low Voltage Low Power Self Biased Latched Comparator with Wide Input Common Mode Range for Biomedical Applications

2015 ◽  
Vol 24 (09) ◽  
pp. 1550134 ◽  
Author(s):  
Seied Zaniar Hoseini ◽  
Johar Abdekhoda ◽  
Kye-Shin Lee
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Average Power ◽  
Threshold Region ◽  
Clock Frequency ◽  
Common Mode ◽  
Common Mode Voltage ◽  
Sensing Applications ◽  
Average Power Consumption

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.

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