A low power 5 MS/s 14 bit switched capacitors digital to analog converter

Author(s):  
L. Gallin-Martel ◽  
D. Dzahini ◽  
F. Rarbi ◽  
O. Rossetto
10.12737/2387 ◽  
2014 ◽  
Vol 6 (3) ◽  
pp. 32-34
Author(s):  
Рембеза ◽  
S. Rembeza ◽  
Кононов ◽  
V. Kononov

The formulated optimal requirements sectional bezkontaktni DAC. Considered are the main technological and frequency limitations sovovych DAC with low power consumption. Suggested 4-bit binary-weighted Zogby differential DAC architecture analogue circuit.


2000 ◽  
Vol 46 (3) ◽  
pp. 896-902 ◽  
Author(s):  
J. Takala ◽  
J. Rostrom ◽  
T. Vaaraniemi ◽  
H. Herranen ◽  
P. Ojala

2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.


2020 ◽  
Vol 29 (3) ◽  
pp. 320-328 ◽  
Author(s):  
Sally Ahmed ◽  
Xuecui Zou ◽  
Nizar Jaber ◽  
Mohammad I. Younis ◽  
Hossein Fariborzi

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