Fully Graph Sensitivity Solution of the Switched Circuits by Two-graph

The most general parameter of the electronic circuit is its sensitivity. Sensitivity analysis helps circuit designers to determine boundaries to predict the variations that a particular design variable will generate in a target specifications, if it differs from what is previously assumed. There are two basic methods for calculating the sensitivity: matrix methods and graph methods. The method described in this article is based on a graph, that contains separate input ad output nodes for each phase. This makes it possible to determine the transmission sensitivity even between partial switching phases. The described fully-graph method is suitable for switched current circuits and switched capacitors circuits, too

Current-mode techniques for UWB frequency synthesizers

This thesis deals with current-mode techniques for ultra-wide band applications. An overview of ultra-wide band (UWB) wireless communications is presented. Two standards for UWB data communications, namely direct-synthesis UWB (DS-UWB) and Multi-band orthogonal frequency division multiplexing (MB-OFDM) UWB are presented. MB-OFDM UWB devices must hop among 14 UWB channels within 9.5 ns, imposing stringent constraints on design of frequency synthesizers. A review of the state-of-the-art frequency synthesizers for MB-OFDM UWB applications is provided. Current-mode phase-locked loops with active inductors and active transformers employed in both loop filters and voltage-controlled oscillators are proposed and their performance in analyzed. Current-mode phase-locked loops decouple the PLL dynamic range from the scaling down of the supply voltage. An active-inductor VCO with both coarse and fine frequency adjustment, a hybrid VCO with a step-down passive transformer loaded with an active inductor, and a hybrid VCO with a step-down passive transformer with a varactor are proposed and their performances are analyzed. These VCOs obtain wide frequency tuning ranges without relying on switched back networks. To meet the timing constraint of UWB frequency synthesizers, Current-mode techniques are further developed for UWB frequency synthesizers. An active inductor with a bank of switched capacitors is proposed to provide fast locking. The bank of switched capacitors eliminates the frequency acquisition locking time of the frequency synthesizer, allowing 9.5 ns phase locking time. The proposed current-mode phase-locked loops, active-inductors oscillators and hybrid oscillators were designed and implemented in TSMC-0.18 μm and IBM-0.13 μm CMOS technologies.

Current-mode techniques for UWB frequency synthesizers

This thesis deals with current-mode techniques for ultra-wide band applications. An overview of ultra-wide band (UWB) wireless communications is presented. Two standards for UWB data communications, namely direct-synthesis UWB (DS-UWB) and Multi-band orthogonal frequency division multiplexing (MB-OFDM) UWB are presented. MB-OFDM UWB devices must hop among 14 UWB channels within 9.5 ns, imposing stringent constraints on design of frequency synthesizers. A review of the state-of-the-art frequency synthesizers for MB-OFDM UWB applications is provided. Current-mode phase-locked loops with active inductors and active transformers employed in both loop filters and voltage-controlled oscillators are proposed and their performance in analyzed. Current-mode phase-locked loops decouple the PLL dynamic range from the scaling down of the supply voltage. An active-inductor VCO with both coarse and fine frequency adjustment, a hybrid VCO with a step-down passive transformer loaded with an active inductor, and a hybrid VCO with a step-down passive transformer with a varactor are proposed and their performances are analyzed. These VCOs obtain wide frequency tuning ranges without relying on switched back networks. To meet the timing constraint of UWB frequency synthesizers, Current-mode techniques are further developed for UWB frequency synthesizers. An active inductor with a bank of switched capacitors is proposed to provide fast locking. The bank of switched capacitors eliminates the frequency acquisition locking time of the frequency synthesizer, allowing 9.5 ns phase locking time. The proposed current-mode phase-locked loops, active-inductors oscillators and hybrid oscillators were designed and implemented in TSMC-0.18 μm and IBM-0.13 μm CMOS technologies.

Conversor Doubler Output Coupled Inductor para Aplicações de Fontes Alternativas

High step-up DC-DC converters are necessary in photovoltaic energy generation, due the low voltage of the panels source. This article propose the Doubler Output Coupled Inductor converter. This converter is based in boost converter and utilize switched capacitors and a coupled inductor to maximize the static voltage gain. The converter achieve a high voltage gain with low turns ratio in the coupled inductor and an acceptable duty cycle. Can highlight the converter utilize low number of components and have low voltage and current stresses in semiconductors. To validate and evaluate the operation of the converter a 200W prototype is simulated.