FPGA-based Matrix Keyboard Common IP Core Design and the Implementation Using Verilog HDL

2017 ◽  
Author(s):  
Weihua Huang ◽  
Licheng Jia
Keyword(s):  
Ip Core ◽  
Verilog Hdl

Design and Implementation of FPGA-Based JPEG Decoding IP Core and its Application in Digital Watermarking

2015 ◽  
Vol 734 ◽  
pp. 621-624
Author(s):  
Qun Xiu Yu ◽  
Shou Ming Zhang ◽  
Chao Wang ◽  
Li Zhi Xie
Keyword(s):  
Integrated Circuits ◽  
Digital Watermarking ◽  
Image Watermarking ◽  
Simulation Software ◽  
Ip Core ◽  
Verilog Hdl ◽  
Jpeg Image ◽  
Design And Implementation ◽  
Watermark Embedding ◽  
Hardware Resource

In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modalism simulation software and would be revised until the simulation results become correct. Finally, the Altera development board EP2C70F896C6N of CycloneII series is used to complete the system design. The results prove that the system can run well, the program which can obtain a larger increase speed in exchange for consuming a little hardware resource does work.

Design and Verification for Data Interface 8051_USB IP Core

2013 ◽  
Vol 321-324 ◽  
pp. 387-390
Author(s):  
Ya Li Chen ◽  
Li Kun Zheng ◽  
Zhe Ying Li
Keyword(s):  
Data Acquisition ◽  
Data Transfer ◽  
Mass Storage ◽  
Ip Core ◽  
Verilog Hdl ◽  
Storage Devices ◽  
Usb Interface ◽  
Efficient Data

A series of portable mass storage devices are arising due to the effective support from USB interface for its special features, such as easy to use, a high transfer speed and low price. 8051_USB IP core is to achieve data acquisition and efficient data transfer to PC. The abstract of USB Protocol is introduced firstly. Then the design and verification of 8051_USB IP core are discussed in detail. Modules of 8051_USB protocol controller are designed with Verilog HDL. The design is simulated with Modelsim.

Design of AD Controller Customized IP Core Based on FPGA

2015 ◽  
Vol 727-728 ◽  
pp. 859-862
Author(s):  
Xiang Sheng Huang
Keyword(s):  
Experimental Results ◽  
Hardware Description Language ◽  
Ip Core ◽  
Verilog Hdl ◽  
Description Language ◽  
C Language ◽  
The Core ◽  
Hardware Description ◽  
Program Interface ◽  
And Control

This design elaborates thedevelopment process of the custom IP core AD9280 controller based on FPGA. Thedesign uses FPGA as the core of the microcontroller, realizes the function ofAD controller by adopting the hardware description language,Verilog HDL and encapsulates it to the custom IP core in the SOPCBuilder. In the NIOS II, the application program interface (API) function ofthe AD controller software is used to access and control the hardware, thesoftware is written by using C language. The experimental results show thatthis custom IP core is feasible and flexible, fully reflects the advantages ofSOPC technology.

Design and Implementation of Reconfigurable Encryption and Decryption System Based on SOPC

2013 ◽  
Vol 347-350 ◽  
pp. 2979-2982
Author(s):  
Qing Fang Zhou ◽  
Qian Huang ◽  
Ying Yuan ◽  
Jun Yang
Keyword(s):  
Hardware Description Language ◽  
Ip Core ◽  
Verilog Hdl ◽  
Description Language ◽  
Nios Ii ◽  
Design And Implementation ◽  
Network Controller ◽  
Encryption And Decryption ◽  
Hardware Description ◽  
Encryption Decryption

The system is based on DES/3DES, AES cipher algorithm as the research object.According to the characteristics of the algorithm, designs a configuration mode which can share resource in space and configurate algorithm in time. Then it uses hardware description language Verilog HDL to realize and optimize the design, and completes a custom reconfigurable DES/3DES/AES encryption/decryption IP core. By SOPC technology, the IP core, Nios II processor, network controller and other function. The design hardware structureis simple, flexibility, security, which can be widely used in the field of informationsecurity.

Research and implementation of OUT endpoint test bench for USB3.0 device controller IP core

2013 ◽  
Vol 26 (7) ◽  
pp. 646-651
Author(s):  
Congzhong Wu ◽  
Le Peng ◽  
Yajun Wang ◽  
Xizhen Yin
Keyword(s):  
Test Bench ◽  
Ip Core

ОСОБЕННОСТИ АРХИТЕКТУРЫ И ОСНОВНЫЕ ХАРАКТЕРИСТИКИ АППАРАТНОГО ВИДЕОКОДЕКА СТАНДАРТА H.264 В СОСТАВЕ МИКРОСХЕМЫ 1892ВМ14Я

2020 ◽  
Vol 96 (3s) ◽  
pp. 89-96
Author(s):  
А.А. Беляев ◽  
Я.Я. Петричкович ◽  
Т.В. Солохина ◽  
И.А. Беляев
Keyword(s):  
Data Flow ◽  
System On Chip ◽  
Video Codec ◽  
Experimental Results ◽  
Video Sequences ◽  
Ip Core ◽  
Performance Measurements ◽  
Synchronization Mechanism ◽  
Architectural Features ◽  
On Chip

Рассмотрены особенности архитектуры и основные характеристики аппаратного видеокодека по стандарту H.264, входящего в состав микросхемы 1892ВМ14Я (MCom-02). Описан механизм синхронизации потоков данных на основе набора флагов событий. Приведены экспериментальные результаты измерения характеристик производительности разработанного видеокодека на реальных видеосюжетах при различных форматах передаваемого изображения. The paper considers main architectural features and characteristics of H.264 hardware video codec IP-core as a part of MCom- 02 system-on-chip (SoC). Bedides, it presents data flow synchronization mechanism based on event flags set, as well as experimental results of performance measurements for the designed video codec IP-core obtained for different video sequences and different image formats.

scholarly journals Decision Tree-Based Adaptive Reconfigurable Cache Scheme

Algorithms ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 176
Author(s):  
Wei Zhu ◽  
Xiaoyang Zeng
Keyword(s):  
Decision Tree ◽  
Adaptive Algorithms ◽  
Memory Access ◽  
Access Time ◽  
Decision Tree Algorithm ◽  
Verilog Hdl ◽  
Tree Model ◽  
Cache Associativity ◽  
Cache Scheme ◽  
Reconfigurable Cache

Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms.

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