The need for integrated passive components which meet the stringent power system requirements imposed by increased data rates, signal path density and challenging power distribution network topologies in integrated systems yield diverse motivations for high density, miniaturized capacitors capable of quickly sourcing large quantities of current. These diverse motivations have led to the realization of high density capacitor structures through the means of several technologies. These structures have been evaluated as high-speed, energy storage devices and their respective fabrication technologies have been closely compared for matching integrated circuit speed and density increase, chip current requirements, low resistance, low leakage current, high capacitance and compatibility with relatively high frequencies of operation (~1GHz). These technologies include devices that utilize pn junctions, Schottky barriers, optimized surface area techniques and the utilization of high dielectric constant (high-K) materials, such as hafnium oxide, as a dielectric layer through the means of atomic layer deposition (ALD). The resulting devices were micro-machined, large surface area, thin, high-density capacitor technologies optimized as embedded passive devices for thin silicon interposers. This work outlines the design, fabrication, simulation and testing of each device revision using standard silicon microfabrication processes and silicon interposer technologies. Consequently, capacitive storage devices were micro-machined with geometries which maximize surface area and exhibit the capability of sourcing 100A of current with a response time greater than 100 A/nsec through the use of thin layered, ALD high-K materials. The simulation and testing of these devices show general agreement when subjected to a standard ring-down procedure. This paper provides descriptions and design challenges encountered during fabrication, testing and integration of these passive devices. In addition, potential device integration and implementation strategies for use in silicon interposers are also provided. The modification and revision of several device generations is documented showing increased device capacitance density, maximized current capabilities and minimized effects of series inductance and resistance. The resulting structures are thin, capacitive devices that may be micro-machined using industry standard Si MEMS processes and are compatible with Si interposer 3D technologies. The subsequent design processes allow integrated passive components to be attached beneath chips in order to maximize system area and minimize the chip real estate required for capacitive energy storage devices.
Layered double hydroxide membrane with high hydroxide conductivity and ion selectivity for energy storage device
