The D defect, which causes the degradation of gate oxide integrities (GOI), can be revealed by Secco etching as flow pattern defect (FPD) in both float zone (FZ) and Czochralski (Cz) silicon crystal or as crystal originated particles (COP) by a multiple-step SC-1 cleaning process. By decreasing the crystal growth rate or high temperature annealing, the FPD density can be reduced, while the D defectsize increased. During the etching, the FPD surface density and etch pit size (FPD #1) increased withthe etch depth, while the wedge shaped contours do not change their positions and curvatures (FIG.l).In this paper, with atomic force microscopy (AFM), a simple model for FPD morphology by non-crystallographic preferential etching, such as Secco etching, was established.One sample wafer (FPD #2) was Secco etched with surface removed by 4 μm (FIG.2). The cross section view shows the FPD has a circular saucer pit and the wedge contours are actually the side surfaces of a terrace structure with very small slopes. Note that the scale in z direction is purposely enhanced in the AFM images. The pit dimensions are listed in TABLE 1.
Performance Analysis of Hybrid Ge-Si Based Mosfet with Different Gate Oxide Thickness and Material
