Morphology and development of flow-pattern defect with extended nonagitated Secco etching

1994 ◽  
Vol 52 ◽  
pp. 868-869
Author(s):  
Y. Pan
Keyword(s):  
Flow Pattern ◽  
Silicon Crystal ◽  
Gate Oxide ◽  
Crystal Growth Rate ◽  
Etch Depth ◽  
Force Microscopy ◽  
Etch Pit ◽  
Float Zone ◽  
Atomic Force ◽  
Multiple Step

The D defect, which causes the degradation of gate oxide integrities (GOI), can be revealed by Secco etching as flow pattern defect (FPD) in both float zone (FZ) and Czochralski (Cz) silicon crystal or as crystal originated particles (COP) by a multiple-step SC-1 cleaning process. By decreasing the crystal growth rate or high temperature annealing, the FPD density can be reduced, while the D defectsize increased. During the etching, the FPD surface density and etch pit size (FPD #1) increased withthe etch depth, while the wedge shaped contours do not change their positions and curvatures (FIG.l).In this paper, with atomic force microscopy (AFM), a simple model for FPD morphology by non-crystallographic preferential etching, such as Secco etching, was established.One sample wafer (FPD #2) was Secco etched with surface removed by 4 μm (FIG.2). The cross section view shows the FPD has a circular saucer pit and the wedge contours are actually the side surfaces of a terrace structure with very small slopes. Note that the scale in z direction is purposely enhanced in the AFM images. The pit dimensions are listed in TABLE 1.

A Novel Electrical Test by C-AFM to Differentiate Gate-to-S/D Gate Oxide Short From Non-Gate Oxide Short Defect in Real Products

2004 ◽  
Author(s):  
Cheng-Piao Lin ◽  
Cheng-Hsu Wu ◽  
Cheng-Chun Ting
Keyword(s):  
Atomic Force Microscopy ◽  
Short Path ◽  
Gate Oxide ◽  
Electrical Test ◽  
Force Microscopy ◽  
Atomic Force ◽  
Gate Oxide Short ◽  
Voltage Contrast

Abstract A method to differentiate Gate-to-S/D Gate Oxide Short from non-Gate Oxide Short defect in real products by analyzing the I-V curves acquired by Conducting-Atomic Force Microscopy (C-AFM) is presented. The method allows not only the correct short path to be identified, but also allows differentiation of gate-to-S/D GOS from non-GOS problems, which cannot be reached by passive voltage contrast (PVC) only.

Subsurface Damage Profile Characterization of Si Wafers with Uv/Millimeter-Wave Technique and Light Scattering Topography

2000 ◽  
Vol 631 ◽  
Author(s):  
Takeo Katoh ◽  
Hideyuki Kondo ◽  
Yoh-Ichiro Ogita ◽  
Ken-Ichi Kobayashi ◽  
Masaki Kurokawa
Keyword(s):  
Light Scattering ◽  
Millimeter Wave ◽  
Silicon Crystal ◽  
Subsurface Damage ◽  
Hydrogen Ion ◽  
Clear Correlation ◽  
Force Microscopy ◽  
Atomic Force ◽  
Wave Technique

ABSTRACTWe have characterized subsurface damage profiles of hydrogen-ion implanted silicon wafers by using a non-contact UV/Millimeter-Wave Technique and Light Scattering Topography (LST). A subsurface damage profile that was less than one micrometer was controlled by chemical mechanical polishing after hydrogen-ion implantation. On the area with the subsurface damage, the Photoconductivity Amplitude (PCA) signals measured by the UV/Millimeter-Wave Technique drastically weakened and the haze values measured by LST increased. A clear correlation has been found between the peak depth of the subsurface damage and the haze value. The spectral analyses of the surface images obtained by Atomic Force Microscopy (AFM) were carried out in order to separate the influences of surface micro roughness and subsurface damage on the haze value. The contribution of subsurface damage to the haze value can be formulated as the convolution of the damage profile and the transparency function of the incident laser in silicon crystal.

High-resolution imaging of biotite dissolution and measurement of activation energy

2008 ◽  
Vol 72 (1) ◽  
pp. 115-120 ◽  
Author(s):  
T. J. McMaster ◽  
M. M. Smits ◽  
S. J. Haward ◽  
J. R. Leake ◽  
S. Banwart ◽  
...  
Keyword(s):  
Activation Energy ◽  
Data Sets ◽  
Ambient Conditions ◽  
Contact Mode ◽  
Force Microscopy ◽  
Etch Pit ◽  
Pit Formation ◽  
Atomic Force ◽  
Diffusion Controlled ◽  
Liquid Cell

AbstractWe have used a direct imaging technique, in situ atomic force microscopy(AFM) to observe the earliest stages of the dissolution of a biotite surface byoxalic acid at temperatures close to ambient conditions, using a speciallydesigned AFM liquid cell and non-invasive intermittent contact mode of operation. From the nm-resolution data sets in x, yand z dimensions, we have measured dissolution rates and determined activation energies for the process as a function of temperature, via a mass-loss calculation. The value of Ea obtained, 49±2 kJ mol-1, appears to be too high to indicate a diffusion-controlled process and is more in line with expectations based on a process limited by the rate of ligand-induced metal cation detachment from the (001) surface. This is consistent with visual observations of the relative rates of etch-pit formation and growth, and accepted knowledge of the biotite crystal structure. Separate calculations based on planar area etch-pit growth, and measurements of etch-pit perimeters confirm this result, and also indicate substantiallyhigher activation energy, up to 80 kJ mol-1, when the edge pits are in an incipient stage.

4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal

2006 ◽  
Vol 527-529 ◽  
pp. 1265-1268 ◽  
Author(s):  
Jeffery B. Fedison ◽  
Chris S. Cowen ◽  
Jerome L. Garrett ◽  
E.T. Downey ◽  
James W. Kretchmer ◽  
...  
Keyword(s):  
Atomic Force Microscopy ◽  
High Temperature ◽  
Room Temperature ◽  
Gate Oxide ◽  
Surface Roughening ◽  
Force Microscopy ◽  
Atomic Force ◽  
N Source ◽  
High Temperature Anneal ◽  
Blocking Voltage

Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).

A Sample Preparation Technique to Localize Gate Oxide Defects in Memory Arrays Using Conducting Atomic Force Microscopy

2011 ◽  
Author(s):  
Lakshminarayanan Lakshmanan ◽  
Lowell Herlinger ◽  
Kathryn Miller
Keyword(s):  
Atomic Force Microscopy ◽  
Sample Preparation ◽  
Gate Oxide ◽  
Silicon On Insulator ◽  
Preparation Technique ◽  
Force Microscopy ◽  
Atomic Force ◽  
Sample Preparation Technique ◽  
Oxide Defects ◽  
Preparation Techniques

Abstract Shrinking gate lengths have led to increased challenges in isolating defects using conventional physical failure analysis methods. Conducting atomic force microscopy (CAFM) has been proven to be a powerful tool to isolate gate oxide defects in silicon-on-insulator devices. Some sample preparation techniques of exposing polysilicon and gate oxide, which were critical to perform CAFM scan, are discussed in this paper.

Backside Imaging and AFM Profiling of Tunnel Oxide, Poly 1, ONO and Poly 2 Layers on Flash Devices

2003 ◽  
Author(s):  
Kaushal Upadhyaya ◽  
Patrice W. Blacker
Keyword(s):  
Flash Memory ◽  
Gate Oxide ◽  
Floating Gate ◽  
Front Side ◽  
Force Microscopy ◽  
Atomic Force ◽  
Metal Interconnects ◽  
Nitride Oxide ◽  
Failure Location ◽  
Scanning Electron

Abstract With increasing density of metal interconnects and shrinking device sizes with each process generation, there has been a growing interest in the Flash failure analysis (FA) community to approach the devices from the backside. Looking at the process layers like Tunnel Oxide, Poly 1 (floating gate), Oxide Nitride Oxide (ONO) and Poly 2 (control gate) from the backside provides useful information about failure location, failure type and failure mechanism which may be obscure from the front side. This work describes a novel combination of mechanical polishes and chemical etches to delayer Intel’s Flash memory devices from the backside to enable viewing of the bottom of the previously mentioned process layers. In addition to Scanning Electron Microscopy (SEM), Atomic Force Microscopy (AFM) has been attempted to gather more information about the surface details. This technique has been used successfully on Intel’s latest 90 nm flash process and has been verified on earlier process generations.

Novel Gox Inspection Methodology in Advanced Silicon Process

2011 ◽  
Author(s):  
Kuo Yu Wang ◽  
Kuo Hsiung Chen ◽  
Jian Chang Lin ◽  
W. S. Wu
Keyword(s):  
Atomic Force Microscopy ◽  
Leakage Current ◽  
Gate Oxide ◽  
New Method ◽  
Electrical Behavior ◽  
Inspection Method ◽  
Force Microscopy ◽  
Atomic Force

Abstract This paper describes a new gate oxide (Gox) inspection method that uses nanoprobing and capacitive-atomic force microscopy (C-AFM) along with optimized etch chemistries and polishing techniques. It presents several examples showing how the new method outperforms conventional Gox inspection approaches in its ability to locate defects such as oxide pin holes and impurities that cause leakage current. It also discusses the electrical behavior of pin holes and soft defects.

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