Abstract
Scan-based test has been the industrial standard method for screening manufacturing defects. Scan chains are vulnerable to most manufacturing defects and process variations. Therefore, chain failures diagnosis is critical for successful yield learning. However, traditional chain diagnosis requires failing masking patterns to identify faulty chains and their fault types for designs with test compression. In other words, it cannot diagnose the chain failures which don't fail the masking chain patterns. Unfortunately, advanced FinFET technologies with more manufacturing challenges and higher process variations may result in more subtle chain timing failures which can't be detected by chain masking patterns. In this work, we present a new debugging methodology, which combines chain diagnosis and tester-based test to effectively diagnose such intermittent chain failures. The proposed methodology is validated on silicon data for one modern large SOC design and successfully identified all scan cells with hold-time issues, which were validated by STA with corrected models. The subsequent mask fixes for these identified hold-time violations resolved this yield issue and dramatically improve the yield.
Low Power Test-Compression for High Test-Quality and Low Test-Data Volume
