Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device
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2017 ◽
Vol 17
(10)
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pp. 7236-7239
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2018 ◽
Vol 57
(4S)
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pp. 04FE17
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2015 ◽
Vol 62
(8)
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pp. 2488-2493
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2018 ◽
Vol 18
(3)
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pp. 1944-1947
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