Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

2013 ◽  
Author(s):  
W. Guo ◽  
V. Moroz ◽  
G. Van der Plas ◽  
M. Choi ◽  
A. Redolfi ◽  
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Keyword(s):  
Cmos Technology ◽  
Through Silicon Via

CMOS TECHNOLOGY FOR CCD VIDEO MEMORIES

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-41-C4-44
Author(s):  
G. J.T. DAVIDS ◽  
P. B. HARTOG ◽  
J. W. SLOTBOOM ◽  
G. STREUTKER ◽  
A. G. van der SIJDE ◽  
...  
Keyword(s):  
Cmos Technology

CMOS-TECHNOLOGY - STATUS, TRENDS AND APPLICATIONS

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-13-C4-22
Author(s):  
F. NEPPL ◽  
H.-J. PFLEIDERER
Keyword(s):  
Cmos Technology

CMOS TECHNOLOGY USING PLASMA NITRIDED OXIDE AS A GATE DIELECTRIC

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-421-C4-424 ◽  
Author(s):  
A. STRABONI ◽  
M. BERENGUER ◽  
B. VUILLERMOZ ◽  
P. DEBENEST ◽  
A. VERNA ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Cmos Technology

Front End of Line Through Silicon Via (TSV) Integration

2008 ◽  
Author(s):  
Subhash L. Shinde ◽  
Todd M. Bauer ◽  
Jordan E. Massad ◽  
Dale L. Hetherington
Keyword(s):  
Through Silicon Via ◽  
Front End

A Region-Based Through-Silicon via Repair Method for Clustered Faults

2017 ◽  
Vol E100.C (12) ◽  
pp. 1108-1117 ◽  
Author(s):  
Tianming NI ◽  
Huaguo LIANG ◽  
Mu NIE ◽  
Xiumin XU ◽  
Aibin YAN ◽  
...  
Keyword(s):  
Through Silicon Via ◽  
Repair Method
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