Investigation into the effect of a “through silicon via”-process on the MOS transistor reliability of a standard 0.13µm CMOS technology

2010 ◽  
Author(s):  
Andreas Martin ◽  
Ludger Borucki ◽  
Hans Reisinger ◽  
Christian Schlunder
Keyword(s):  
Cmos Technology ◽  
Through Silicon Via ◽  
Mos Transistor ◽  
Transistor Reliability

Effective Circuit Design Methodologies for Standby Leakage Power Reduction

2020 ◽  
Vol 12 (2) ◽  
pp. 168-172
Author(s):  
Manish Kumar ◽  
Md. Anwar Hussain ◽  
Sajal K. Paul
Keyword(s):  
Circuit Design ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Logic Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Model Parameters ◽  
Mos Transistor ◽  
Design Methodologies ◽  
Transistor Model

This paper presents circuit level design methodologies for significantly reducing the standby leakage power. Layout of different CMOS logic circuits such as a 2-input XOR, a 2-input XNOR, and a 4-input XNOR are designed and simulated by using BSIM4 MOS transistor model parameters. Layout simulations are done at a supply voltage of 0.4 V in 45 nm CMOS technology. Logic circuits designed by using the proposed circuit design methodologies proved to be effective in minimizing the standby leakage power. All layout design and simulation of the circuits are carried out by using Microwind EDA software (version 3.1).

scholarly journals Prototyping of an All-pMOS-Based Cross-Coupled Voltage Multiplier in Single-Well CMOS Technology for Energy Harvesting Utilizing a Gastric Acid Battery

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 804
Author(s):  
Shinya Yoshida ◽  
Hiroshi Miyaguchi ◽  
Tsutomu Nakamura
Keyword(s):  
Energy Harvesting ◽  
Gastric Acid ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
The Body ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Mos Transistor ◽  
Voltage Multiplier ◽  
Single Well

A gastric acid battery and its charge storage in a capacitor are a simple and safe method to provide a power source to an ingestible device. For that method, the electromotive force of the battery should be boosted for storing a large amount of energy. In this study, we have proposed an all-p-channel metal-oxide semiconductor (pMOS)-based cross-coupled voltage multiplier (CCVM) utilizing single-well CMOS technology to achieve a voltage boosting higher than from a conventional complementary MOS (CMOS) CCVM. We prototyped a custom integrated circuit (IC) implemented with the above CCVMs and a ring oscillator as a clock source. The characterization experiment demonstrated that our proposed pMOS-based CCVM can boost the input voltage higher because it avoids the body effect problem resulting from an n-channel MOS transistor. This circuit was also demonstrated to significantly reduce the circuit area on the IC, which is advantageous as it reduces the chip size or provides an area for other functional circuits. This simple circuit structure based on mature and low-cost technologies matches well with disposal applications such as an ingestible device. We believe that this pMOS-based CCVM has the potential to become a useful energy harvesting circuit for ingestible devices.

scholarly journals Surface micromachining of a micro electromechanical inertial transducer based on commercially available Floating Gate Transistor technology

2018 ◽  
Vol 31 (3) ◽  
pp. 48-51
Author(s):  
Griselda Stephany Abarca-Jiménez ◽  
Gabriel Romero-Paredes Rubio ◽  
Mario Alfredo Reyes-Barranca ◽  
Miguel Ángel Alemán-Arce ◽  
Jacobo Esteban Munguía-Cervantes ◽  
...  
Keyword(s):  
Inertial Sensor ◽  
Sacrificial Layer ◽  
Cmos Technology ◽  
Floating Gate ◽  
Surface Micromachining ◽  
Design Rules ◽  
Fully Integrated ◽  
Mos Transistor ◽  
Processing Step ◽  
Floating Gate Transistor

This work presents the results of different surface micromachining processes done on a chip from On Semiconductor 0.5 µm commercially available CMOS technology. The intended objective is to fabricate a MEMS inertial transducer in a monolithic substrate, as the electronics for signal processing are based on a Floating Gate MOS transistor, fully integrated in the electromechanical structure. According to the available layers and design rules from the foundry, an inertial sensor chip was designed and fabricated, except the last post–processing step, i.e., the removal of the sacrificial layer and thus releasing the inertial structure based on a surface micromachining process, allowing the completed device to behave as designed.

NEGATIVE RESISTANCE ACTIVE RESISTOR WITH IMPROVED LINEARITY AND FREQUENCY RESPONSE

2009 ◽  
Vol 18 (01) ◽  
pp. 1-10 ◽  
Author(s):  
COSMIN POPA
Keyword(s):  
Frequency Response ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Original Method ◽  
Order Effects ◽  
Mos Transistors ◽  
Mos Transistor ◽  
Saturation Region ◽  
Linear Differential

An original active resistor circuit will be presented. The main advantages of the new proposed implementations are the improved linearity, small area consumption and improved frequency response. An original technique for linearizing the I(V) characteristic of the active resistor will be proposed, based on the utilization of a new linear differential amplifier, and on a current-pass circuit. The linearization of the original differential structure is achieved by compensating the quadratic characteristic of the MOS transistor operating in the saturation region by an original square-root circuit. The errors introduced by the second-order effects will be strongly reduced, while the circuit frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. In order to design a circuit having a negative equivalent resistance, an original method specific to the proposed implementation of the active resistor circuit will be presented. The circuit is implemented in 0.35 μm CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error under a percent for an extended input range (± 500 mV) and a small value of the supply voltage (± 3 V).

LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR

2009 ◽  
Vol 18 (03) ◽  
pp. 519-534 ◽  
Author(s):  
COSMIN POPA
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Mos Transistor ◽  
Curvature Correction ◽  
Current Consumption ◽  
Correction Technique

Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 < t < 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 < t < 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.

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