A low power 2.4-GHz CMOS direct-conversion transmitter for IEEE 802.15.4

Author(s):  
Chihoon Choi ◽  
Joonwoo Choi ◽  
Minsu Kim ◽  
Hojong Park ◽  
Ilku Nam
2007 ◽  
Vol 55 (4) ◽  
pp. 682-689 ◽  
Author(s):  
Ilku Nam ◽  
Kyudon Choi ◽  
Joonhee Lee ◽  
Hyouk-Kyu Cha ◽  
Bo-Ik Seo ◽  
...  

2006 ◽  
Vol 54 (12) ◽  
pp. 4062-4071 ◽  
Author(s):  
Trung-Kien Nguyen ◽  
Vladimir Krizhanovskii ◽  
Jeongseon Lee ◽  
Seok-Kyun Han ◽  
Sang-Gug Lee ◽  
...  

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  

2021 ◽  
Vol 3 (4) ◽  
Author(s):  
S. Chrisben Gladson ◽  
Adith Hari Narayana ◽  
V. Thenmozhi ◽  
M. Bhaskar

AbstractDue to the increased processing data rates, which is required in applications such as fifth-generation (5G) wireless networks, the battery power will discharge rapidly. Hence, there is a need for the design of novel circuit topologies to cater the demand of ultra-low voltage and low power operation. In this paper, a low-noise amplifier (LNA) operating at ultra-low voltage is proposed to address the demands of battery-powered communication devices. The LNA dual shunt peaking and has two modes of operation. In low-power mode (Mode-I), the LNA achieves a high gain ($$S21$$ S 21 ) of 18.87 dB, minimum noise figure ($${NF}_{min.}$$ NF m i n . ) of 2.5 dB in the − 3 dB frequency range of 2.3–2.9 GHz, and third-order intercept point (IIP3) of − 7.9dBm when operating at 0.6 V supply. In high-power mode (Mode-II), the achieved gain, NF, and IIP3 are 21.36 dB, 2.3 dB, and 13.78dBm respectively when operating at 1 V supply. The proposed LNA is implemented in UMC 180 nm CMOS process technology with a core area of $$0.40{\mathrm{ mm}}^{2}$$ 0.40 mm 2 and the post-layout validation is performed using Cadence SpectreRF circuit simulator.


2019 ◽  
Vol 6 (2) ◽  
pp. 3437-3447 ◽  
Author(s):  
Abdullah Zubair Mohammed ◽  
Ajay Kumar Nain ◽  
Jagadish Bandaru ◽  
Ajay Kumar ◽  
D. Santhosh Reddy ◽  
...  

2016 ◽  
Vol 5 (3) ◽  
pp. 50 ◽  
Author(s):  
M. Shah ◽  
S. Gupta

Direct Conversion Receiver is the choice of the today’s designer for low power compact wireless receiver. DCR is attractive due to low power, small size and highly monolithic integratable structure, but distortions affect its performance.  I/Q mismatch is the one of the major distortion which is responsible for performance degradation.  In this paper, a novel method for Direct Conversion Receiver is suggested, which makes it insensitive to the I/Q mismatch. Here the classical homodyne architecture is modified to nullify effect of I/Q mismatch. The proposed method can be implemented in the Digital Signal Processing (DSP) back-end section also.  This feature makes it acceptable in the already designed/functioning classical homodyne architecture based receiver.


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