Various designs of compliant interconnects are being pursued in universities and industry to accommodate the coefficient of thermal expansion (CTE) mismatch between die and substrate or substrate and board. Although such interconnects are able to mechanically decouple the components, electrical parasitics of compliant interconnects are often high compared to the electrical parasitics of solder bump or solder ball interconnects. This increase in electrical parasitics is due to the fact that compliant interconnects typically having longer path lengths and smaller cross-sectional areas to provide compliance, which in turn, increases their electrical parasitics. In this paper, we present a mixed array of compliant interconnects as a tradeoff between mechanical compliance and electrical parasitics. In the proposed implementation, the die area is subdivided into three regions where high compliance, medium-compliance, and low-compliance interconnect variants are situated in the outer, middle, and inner regions of the die, respectively. By introducing the low-compliance variants into the assembly, interconnects with greatly reduced electrical parasitics can be used as power/ground interconnects, while the high-compliance interconnects, situated near the die edges, can be used as signal interconnects. This paper demonstrates the implementation of this configuration and also presents the experimental characterization of such heterogeneous array of interconnects.
Mechanical characterization of polysilicon cantilevers using a thermo-mechanical test chip fabricated with a combined bulk/surface micromachining technique
