Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip–solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip–solder layer; model II, chip–solder layer and copper layer; and model III, chip–solder layer and DBC substrate) were developed. The 25–150 °C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip–solder interface was calculated. The results of model I showed that the chip–solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip–solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.

Effect of Polymer Liners in Different Via Shapes: Impact on Crosstalk Induced Delay

The performance of a through silicon via (TSV) based 3D integrated circuit technology is primarily dependent on the choice of an appropriate liner material. The most commonly used liner material SiO2 is undergoing considerable reliability challenges such as coefficient of thermal expansion (CTE) mismatch, scallop formation, and interfacial delamination related problems. Therefore, TSVs employed with a polymer liner have achieved significant attention in recent years due to their low dielectric constant and excellent step coverage along the via surface that can effectively reduce thermal stress and crosstalk induced delay. This paper presents a comprehensive and accurate RLGC model for different via shapes considering the impact of various liner materials on the crosstalk induced delay. Considering an accurate via geometry and material properties at 32 nm and 45 nm technology, the proposed equivalent RLGC parameters include the cumulative effects of TSV metal, liner, bump, and the silicon substrate. The aforementioned parameters are used to model a novel T-type equivalent electrical network of cylindrical, tapered, and coaxial TSVs considering a coupled driver-via-load (DVL) setup. The proposed equivalent models of different via shapes are used to demonstrate the worst-case crosstalk induced delay in TSVs under the influence of various liner materials. Considering a tapered TSV, a significant improvement in crosstalk induced delay at 32 nm w.r.t. 45 nm technology is observed as 53.5%, 33.76%, and 19.12% at aspect ratios of 2.4, 3, and 4, respectively for the BCB liner.

Dynamic warpage simulation of molded PCB under reflow process

Purpose This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes. Design/methodology/approach This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results. Findings Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature. Research limitations/implications The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials. Practical implications This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process. Social implications The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment. Originality/value The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.

Design and Introduction of Thermal Collection Network (TCN) for the Thermal Management in 3-D IC Structures

Power in Watts of the chip, per unit area is growing exponentially in the electronic industry. At the same time, thermal problems becoming side effects of huge power consumption. Continuous efforts are getting made to remove the thermal problems of electronic packaging and systems. Thermal problems if not alleviated or suppressed, will lead the dielectric breakdown, electromigration, material creep, thermal cycling, chemical reactions, board warpage, performance drift, indirect heating, and many more problems. Likewise, a dedicated Power Delivery/distribution Network (PDN), can deliver the power to the chip base, this paper has introduced a new methodology of a dedicated Thermal Collection Network (TCN) in the same Back End Of Line (BEOL) area of the System in Package (SiP), System on Chip (SOC) and any other power-consuming chips. Adding a Thermal Through Silicon Via (TTSV) is another advantage in it. Using such an apparatus or methodology connected to TTSV will quickly pump-up the thermal energy to the heat-sink-fan assembly. Hence, preempting of heat from its sources can manage the thermal problems inside the chips or 3-D IC structures. The methodology uses the same copper metal stripes inside the Inter-Layer/Level-Dielectric (ILD), which will not lead to any extra copper to introduce more Coefficient of Thermal Efficiency (CTE) mismatch problems. It would be considered as one among the other metal stripes. The experimental results using the Finite Element Method (FEM) tool shown that 32% heat suction occurs in the TCNs, in monolithic ICs, and 11% in 3-D IC structures, compared to without such an approach. The junction temperature remained at 35%, with and without such an approach, in 3-D IC structures. This might lead to a new methodology for designing electronic chips and 3-D IC structures, in the future.

Investigation on Die Crack in a Stacked Die Package Using Finite Element Analysis

Die crack is one of the problems in stacked die semiconductor packages. As silicon dies become thinner in such packages due to miniaturization requirement, the tendency to have die crack increases. This study presents the investigation done on a die crack issue in a stacked die package using finite element analysis (FEA). The die stress induced during the package assembly processes from die attach to package strip reflow was analyzed and compared with the actual die crack failure in terms of the location of maximum die stress at unit level as well as strip level. Stresses in the die due to coefficient of thermal expansion (CTE) mismatch of the package component materials and mechanical bending of the package in strip format were taken into consideration. Comparison of the die stress with actual die crack pointed to strip bending as the cause of the problem and not CTE mismatch. It was found that the die crack was not due to the thermal processes involved during package assembly. This study showed that analyzing die stress using FEA could help identify the root cause of a die crack problem during the stacked die package assembly and manufacturing as crack occurs at locations of maximum stress. The die crack mechanism can also be understood through FEA simulation and such understanding is very important in coming up with robust solution.

Tailoring of Thermo-Mechanical Properties of Hybrid Composite-Metal Bonded Joints

Metallic substrates and polymer adhesive in composite-metal joints have a relatively large coefficient of thermal expansion (CTE) mismatch, which is a barrier in the growing market of electric vehicles and their battery structures. It is reported that adding carbon nanotubes (CNTs) to the adhesive reduces the CTE of the CNT-enhanced polymer adhesive multi-material system, and therefore when used in adhesively bonded joints it would, theoretically, result in low CTE mismatch in the joint system. The current article presents the influence of two specific mass ratios of CNTs on the CTE of the enhanced polymer. It was observed that the addition of 1.0 wt% and 2.68 wt% of multi-walled CNTs (MWCNTs) decreased the CTE of the polymer adhesive from 7.5×10−5 °C−1 (pristine level) to 5.87×10−5 °C−1 and 4.43×10−5 °C−1, respectively, by 22% and 41% reductions.

High-Temperature Oxidation of NiAlCr–Ca and NiAlCr–Sr Alloys in Air

In this study, interrupted oxidation behavior of synthetic NiAlCr–Ca (Ca = 0.3, 1.4, 2 at.%) and NiAlCr–Sr (Sr = 0.4 at.%) alloys in the air at 1027 °C for 192 h was investigated. Parabolic rate constants (kp) showed that the Sr-containing alloy exhibited the best oxidation resistance among the alloys investigated in this study. The oxide scale formed on the Sr-containing alloy was composed of α-Al2O3 phase with Sr-rich nodules. Increasing the Ca concentration in the alloys was found to reduce the oxidation resistance due to the formation of non-protective Ca-rich complex oxides and consumption of α-Al2O3 scale by the reaction between Al2O3 and CaO. The Ca-rich complex oxides were initially formed on the Ca-rich interdendritic region and grew with time. Very little scale spallation was observed for the Sr-containing alloy, while it was notable for 0.3 at.% Ca-containing alloy. Spallation was attributed to the coefficient of thermal expansion (CTE) mismatch arisen from the formation of CaAl4O7 phase, a compound with a very low CTE.

Tailoring of Thermo-Mechanical Properties of Hybrid Composite-Metal Bonded Joints

Metallic substrates and polymer adhesive in composite-metal joints have a relatively large coefficient of thermal expansion (CTE) mismatch, which is a barrier in the growing market of electric vehicles and their battery structures. It is reported that adding carbon nanotubes (CNTs) to the adhesive reduces the CTE of the CNT enhanced polymer adhesive multi-material system, therefore when used in adhesively bonded joints it would, theoretically, result in low CTE mismatch in the joint system. The current article presents the influence of two specific mass ratios of CNTs on the CTE of the enhanced polymer. It was observed that the addition of 1.0 wt% and 2.68 wt% of multi-walled CNTs (MWCNTs) decreased the CTE of the polymer adhesive from 7.5e-5 1/C (pristine level) to 5.87e-5 1/C and 4.43e-5 1/C, respectively by 22% and 41% reduction. The reduction in the CTE was predicted, theoretically, which showed that CTE should have been reduced to 3.6e-5 1/C (52% reduction) and 1.4e-5 1/C (81% reduction). This may be due to the fact that, Raman spectroscopy of the MWCNTs identified defects in the raw material, and scanning electron microscopy (SEM) identified agglomeration of MWCNTs on the surface and cross-section of the modified polymers.

Effect of Epoxy Molding Compound Material and Roughness Leadframe to Integrated Circuit Package for Automotive Devices

This research studied about an effect of epoxy molding compound material and roughness leadframe of integrated circuit package for automotive device. In manufacturing process, the epoxy molding compound material and leadframe roughness are main factors that effect to coefficient of thermal expansion (CTE) and reliability for automotive device package with no delamination in high temperature application. In experiment, two types of epoxy molding compound materials were studied and compared between standard and roughened leadframe for quad flat non lead (QFN) package. For reliability test, the epoxy molding compound materials type A and type B with different leadframe were analyzed with moisture sensitivity level 1 to observe delamination inside packages. The results showed that CTE of epoxy molding compound material type A is less CTE mismatch than that of epoxy molding compound material type B with both standard and roughness leadframe. Moreover, the results also found no delamination for epoxy molding compound material type A with roughened leadframe. In addition, both epoxy molding compound materials showed significant delamination inside packages with standard leadframe.

Reliability Impacts on Flip Chip Packages: Moisture Resistance, Mechanical Integrity and Photo-Sensitive Polyimide (PSPI) Passivation

In this paper, the effects of moisture sensitivity during preconditioning (30 °C/60% RH, 192 hours) tests and material property changes after reliability stressing on flip chip chip-scale package (FCCSP) were comprehensively investigated by various experimental data as well as theoretical explanation. Since the integrity of FCCSP is dependent on the mechanical integrity of underfill and PCB used in package assembly process, deep insight was given on the material properties in order to understand degradation mechanism induced by the combined stresses of preconditioning test and environmental stresses in a sequence. As a result of DOE (Design of Experiment) for 2 different PCB, failures were found only in J PCB because of a large CTE change before and after moisture absorption. After moisture absorption, large CTE change from 27.78 to 32.04 of J PCB could aggravate the thermal mismatch between a PCB and an underfill, it caused shear displacement by more than 2,309 ppm in the interface. According to the DOE for underfill, we verified that higher modulus underfill could improve the reliability of flip chip packages. Based on our works, we recommend the optimized value for underfill modulus is from 8 GPa to 12 GPa. We explained logically two different failure mechanisms of delamination. One is induced by CTE mismatch of PCB, and the other is by underfill modulus by means of electron microscope. Finally, as to reliability concerns of moisture resistance arisen from the absence of the photo-sensitive polyimide (PSPI) passivation layer, we demonstrated that potential risk is minimal if FCCSP is assembled with an appropriate underfill as well as PCB.