Effect of rapid thermal shock cycle on the thermomechanical reliability of 20Sn-80Pb solder bumps

The influence of rapid thermal shock(RTS) cycles on 20Sn-80Pb solder bumps was studied. In the study, 20Sn-80Pb solder bumps were prepared by desktop nitrogen lead-free reflow soldering machine. The prepared 20Sn-80Pb solder bumps were used for RTS test in the temperature rang of 0°C ~ 150°C. One cycle of RTS is 24 seconds, and the temperature rise and fall rate of RTS is 12.5 C/s. The result indicated that when the cycle of RTS reached 1500T (here T is cycle, the same below), the shear strength of Sn-80Pb solder bump dropped by drastically 48.6%. Whereas, when the cycle of RTS reached 5500T, 20Sn-80Pb solder bumps’ shear strength decreased to 18.35 MPa, which increased by 7.5% compared with that of l6.97 MPa at 4500T. With the increase of RTS cycles, 20Sn-80Pb solder bumps’ shear strength was a decreasing trend and the fracture mechanism changed from ductile fracture to ductile-brittle mixed fracture, which could be subject to the thickening of the interfaical IMCs and the stress concentration caused by the growth of interfacial IMCs. To understand the changes of the mechanical properties of 20Sn-80Pb solder bumps, the influences of RTS on the crack and interfacial IMC of 20Sn-80Pb solder bumps were studied in details.

Microstructural Analysis of Solder Bump Fabricated by Sn Electroplating on a PCB Substrate

To manufacture finer solder bumps, the SR and DFR patterns were filled using a Sn electroplating process instead of the microball process currently used in BGA technology, and the solder bump shape was fabricated through a reflow process. The microstructure of the solder bump was investigated by EBSD and TEM measurements. The EBSD results showed that the grain size of the Sn structure became finer after the reflow treatment and a scallop shape of Cu₆Sn₅ was formed on the Cu UBM. However, the Cu₃Sn phase was difficult to measure in the EBSD measurement. The Cu₃Sn compound could be investigated with TEM analysis. The Cu₃Sn phase also existed in the Sn region, with a size of several tens of nanometers, due to the eutectic reaction. The volume fraction of the Cu₆Sn₅ phase in the Sn region could be calculated from the TEM image, and the concentration of copper dissolved in the liquid tin during the reflow process could be estimated from the volume fraction. It was possible to observe the Cu₃Sn and Cu₆Sn₅ lattice images through high resolution TEM analysis, but it was difficult to observe the lattice coherency between the two phases because both were polycrystalline. Based on the results of this study, it is expected that solder bumps with a diameter of less than 100 µm can be robustly manufactured through the Sn electroplating process.

Simulation and Experimental study on IMS (Injection Molded Solder) bumping with expanded resist patterning for reinforcement of fine-pitch capability

Injection Molded Solder (IMS) process has been developed as one of the advanced micro-bumps forming techniques. This paper presents a novel IMS process utilizing a double-layer resist patterning with expanded opening for the reduction of required injection pressure. It consists of upper resist layer with larger opening diameter than lower resist opening. With this configuration, necessary injection pressure is adjusted to upper resist size, while lower layer determines the position and the size of fabricated bump. Furthermore, two different types of resist opening shape, an isolated opening and connected opening are proposed and evaluated in this study from both simulation and experimental perspective. For simulation, CFD analysis is performed to demonstrate the behavior of liquid molten solder flow and its bump forming process. It is revealed that solder bump was successfully formed in accordance with theoretical bump size in both designs. However, the result indicates that insufficient non-wetting property of resist material could lead solder bridging between adjacent bumps in connected design. Experiment is also conducted using the novel resist structure with the dimension correlated to the simulation model which has lower resist diameter of 10 μm, upper resist diameter of 15 μm, and the pitch of 20 μm. IMS is operated and it is confirmed that the uniform bumps can be favorably formed without any defects.

Solder Bump Joint Failure Investigation: From Sample Preparation to Advanced Structural Characterizations and Strain Measurements

This paper describes the detailed sample preparation of a solder joint at the level between a semiconductor package and board. Different sample preparation techniques are described and compared. Preparing and targeting a large sample area containing multiple solder bumps is discussed. The sample preparation methods will then be confirmed by advanced structural characterization and strain measurement. The presence of strain is associated with the development of cracks and delamination at the solder joint interface.

CFD Analysis of Molten Solder Flow Behavior and Bridging Mechanism During Solder Bump Formation

Technology of fine pitch interconnect with lead-free solder joint has been developed to enhance the performance of flip-chip high density packages. This study presents an investigation of solder bump forming behavior by means of CFD simulation analysis. The flow motion of molten solder is analyzed with 3D model we developed, and the simulation result is validated with the experiment. Moreover, the investigation of factors affecting solder bridging across adjacent pads is also performed. It is revealed that wettability between liquid solder and organic insulator, which is represented as contact angle in the calculation has large effect on the solder bridging phenomena. The simulation result suggests that worsening the wettability of the insulator can reduce the occurrence of bridging.

Control of Solder Bump Growing Morphology in Lead Free Plating

Plating Solder bump is one of the key enabling technologies for flip chip assembly methodology. Flip chip assembly has advanced to support higher levels of interconnect and small feature sizes. Electroplating is a very promising technology for finer bump features when compared with solder printing and ball mounting. Hence, the plated-solder bump morphology is quite important for process quality control and design realization. This paper aims to study the plated solder behavior from as-plated mushroom structure to after reflowed bump stage photoresist sizing. In addition, this activity will consider the full bumping process integration relative to the electroplated solder bump design rules.