Thermal Behaviors of Passively-Cooled Hybrid Fin Heat Sinks for Lightweight and High Performance Thermal Management

A computational study is conducted to explore thermal performances of natural convection hybrid fin heat sinks (HF HSs). The proposed HF HSs are a hollow hybrid fin heat sink (HHF HS) and a solid hybrid fin heat sink (SHF HS). Parametric effects such as a fin spacing, an internal channel diameter, a heat dissipation on the performance of HF HSs are investigated by CFD analysis. Study results show that the thermal resistance of the HS increases while the mass-multiplied thermal resistance of the HS decreases associated with the increase of the channel diameter. The results also shows the thermal resistance of the SHF HS is 13% smaller, and the mass-multiplied thermal resistance of the HHF HS is 32% smaller compared with the pin fin heat sink (PF HS). These interesting results are mainly due to integrated effects of the mass-reduction, the surface area enhancement, and the heat pumping via the internal channel. Such better performances of HF HSs show the feasibility of alternatives to the conventional PF HS especially for passive cooling of LED lighting modules.

Electrical-Thermal-Reliability Co-Design for TSV-Based 3D-ICs

This paper presents an electrical-thermal-reliability co-design technique for TSV-based 3D-ICs. Although TSV-based 3D-IC shows significant electrical performance improvement compared to traditional 2D circuit, researchers have reported strong electromigration (EM) in TSVs, which is induced by the thermal mechanical stress and the local temperature hotspot. We argue that rather than addressing 3D-IC’s EM issue after the IC designing phase, the designer should be aware of the circuit’s thermal and EM properties during the IC designing phase. For example, one should be aware that the TSVs establish vertical heat conduction path thus changing the chip’s thermal profile and also produce significant thermal mechanical stress to the nearby TSVs, which deteriorates other TSV’s EM reliability. Therefore, the number and location of TSVs play a crucial role in deciding 3D-IC’s electrical performance, changing its thermal profile, and affecting its EM-reliability. We investigate the TSV placement problem, in order to improve 3D-IC’s electrical performance and enhance its thermal-mechanical reliability. We derive and validate simple but accurate thermal and EM models for 3D-IC, which replace the current employed time-consuming finite-element-method (FEM) based simulation. Based on these models, we propose a systematic optimization flow to solve this TSV placement problem. Results show that compared to conventional performance-centered technique, our design methodology achieves 3.24x longer EM-lifetime, with only 1% performance degradation.

Microprocessor Silicon Die Temperature Prediction by Simplified Boundary Conditions

The thermal network method has a long history with thermal design of electronic equipment. In particular, a one-dimensional thermal network is useful to know the temperature and heat transfer rate along each heat transfer path. It also saves computation time and/or computation resources to obtain target temperature. However, unlike three-dimensional thermal simulation with fine pitch grids and a three-dimensional thermal network with sufficient numbers of nodes, a traditional one-dimensional thermal network cannot predict the temperature of a microprocessor silicon die hot spot with sufficient accuracy in a three-dimensional domain analysis. Therefore, this paper introduces a one-dimensional thermal network with average temperature nodes. Thermal resistance values need to be obtained to calculate target temperature in a thermal network. For this purpose, thermal resistance calculation methodology with simplified boundary conditions, which calculates thermal resistance values from an analytical solution, is also introduced in this paper. The effectiveness of the methodology is explored with a simple model of the microprocessor system. The calculated result by the methodology is compared to a three-dimensional heat conduction simulation result. It is found that the introduced technique matches the three-dimensional heat conduction simulation result well.

Rack Server Solution in Data Center

With the advent of big data and cloud computing solutions, enterprise demand for servers is increasing. There is especially high growth for Intel based x86 server platforms. Today’s datacenters are in constant pursuit of high performance/high availability computing solutions coupled with low power consumption and low heat generation and the ability to manage all of this through advanced telemetry data gathering. This paper showcases one such solution of an updated rack and server architecture that promises such improvements. The ability to manage server and data center power consumption and cooling more completely is critical in effectively managing datacenter costs and reducing the PUE in the data center. Traditional Intel based 1U and 2U form factor servers have existed in the data center for decades. These general purpose x86 server designs by the major OEM’s are, for all practical purposes, very similar in their power consumption and thermal output. Power supplies and thermal designs for server in the past have not been optimized for high efficiency. In addition, IT managers need to know more information about servers in order to optimize data center cooling and power use, an improved server/rack design needs to be built to take advantage of more efficient power supplies or PDU’s and more efficient means of cooling server compute resources than from traditional internal server fans. This is the constant pursuit of corporations looking at new ways to improving efficiency and gaining a competitive advantage. A new way to optimize power consumption and improve cooling is a complete redesign of the traditional server rack. Extracting internal server power supplies and server fans and centralizing these within the rack aims to achieve this goal. This type of design achieves an entirely new low power target by utilizing centralized, high efficiency PDU’s that power all servers within the rack. Cooling is improved by also utilizing large efficient rack based fans for airflow to all servers. Also, opening up the server design is to allow greater airflow across server components for improved cooling. This centralized power supply breaks through the traditional server power limits. Rack based PDU’s can adjust the power efficiency to a more optimum point. Combine this with the use of online + offline modes within one single power supply. Cold backup makes data center power to achieve optimal power efficiency. In addition, unifying the mechanical structure and thermal definitions within the rack solution for server cooling and PSU information allows IT to collect all server power and thermal information centrally for improved ease in analyzing and processing.

Steady State and Transient Comparison of Perimeter and Row-Based Cooling Employing Controlled Cooling Curves

The perpetual increase of data processing has led to an ever increasing need for power and in turn to greater cooling challenges. High density (HD) IT loads have necessitated more aggressive and direct approaches of cooling as opposed to the legacy approach by the utilization of row-based cooling. In-row cooler systems are placed between the racks aligned with row orientation; they offer cool air to the IT equipment more directly and effectively. Following a horizontal airflow pattern and typically occupying 50% of a rack’s width; in-row cooling can be the main source of cooling in the data center or can work jointly with perimeter cooling. Another important development is the use of containment systems since they reduce mixing of hot and cold air in the facility. Both in-row technology and containment can be combined to form a very effective cooling solution for HD data centers. This current study numerically investigates the behavior of in-row coolers in cold aisle containment (CAC) vs. perimeter cooling scheme. Also, we address the steady state performance for both systems, this includes manufacturer’s specifications such as heat exchanger performance and cooling coil capacity. A brief failure scenario is then run, and duration of ride through time in the case of row-based cooling system failure is compared to raised floor perimeter cooling with containment. Non-raised floor cooling schemes will reduce the air volumetric storage of the whole facility (in this small data center cell it is about a 20% reduction). Also, the varying thermal inertia between the typical in-row and perimeter cooling units is of decisive importance. The CFD model is validated using a new data center laboratory at Binghamton University with perimeter cooling. This data center consists of one main Liebert cooling unit, 46 perforated tiles with 22% open area, 40 racks distributed on three main cold aisles C and D. A computational slice is taken of the data center to generalize results. Cold aisle C consists of 16 rack and 18 perforated tiles with containment installed. In-row coolers are then added to the CFD model. Fixed IT load is maintained throughout the simulation and steady state comparisons are built between the legacy and row-based cooling schemes. An empirically obtained flow curve method is used to capture the flow-pressure correlation for flow devices. Performance scenarios were parametrically analyzed for the following cases: (a) Perimeter cooling in CAC, (b) In-row cooling in CAC. Results showed that in-row coolers increased the efficiency of supply air flow utilization since the floor leakage was eliminated, and higher pressure build up in CAC were observed. This reduced the rack recirculation when compared to the perimeter cooled case. However, the heat exchanger size demonstrated the limitation of the in-row to maintain controlled set point at increased air flow conditions. For the pump failure scenario, experimental data provided by Emerson labs were used to capture the thermal inertia effect of the cooling coils for in-row and perimeter unit, perimeter cooled system proved to have longer ride through time.

Compact Thermal Modeling Methodology for Active and Thermal Bumps in 3D Microelectronic Packages

Accurate estimation of the thermal conductivity of logic-memory and memory-memory interfaces, between stacked die in 3D microelectronic packages, is key to effective design and early estimates of performance and reliability. Typically, interconnect layers contain hundreds to a few thousands of bumps. Hence lumped/compact modeling of this interfacial layer is essential to reduce computational time and complexity. The typical approach to this lumped modeling is to estimate the effective conductivity of the layer by assuming the bumps and underfill regions can be modelled as parallel thermal resistances (referred to as the volumetric method). This work demonstrates that the volumetric method can significantly underpredict 3D stack thermal resistance and junction temperatures. An alternative method-referred to as the single bump method-of estimation of the thermal conductivity of interconnect layers in 3D stacked-die packages is presented. Studies demonstrate that the proposed single bump method captures the heat transfer in these interfaces accurately. Validation of the single bump modeling is presented by comparing the single bump and volumetric methods with fully discretized models. This comparison also demonstrates that the prevalent volumetric method overestimates the effective thermal conductivity of the interface, while the single bump approach results in more accurate assessment of 3D stack resistance.

Experimental Characterization of the Vertical and Lateral Heat Transfer in 3D-SIC Packages

In this paper, we present the experimental characterization of 3D packages using a dedicated stackable test chip. An advanced CMOS test chip with programmable power distribution has been designed, fabricated, stacked and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling, and soldered to the PCB. Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the epoxy mold compound and the die-die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the trade-off between the stand-off height reduction and the underfill thermal conductivity increase in order to reduce the inter die thermal resistance.

Understanding the True Total Cost of Ownership of Water Cooling for Data Centers

The generation-to-generation IT performance and density demands continue to drive innovation in data center cooling technologies. For many applications, the ability to efficiently deliver cooling via traditional chilled air cooling approaches has become inadequate. Water cooling has been used in data centers for more than 50 years to improve heat dissipation, boost performance and increase efficiency. While water cooling can undoubtedly have a higher initial capital cost, water cooling can be very cost effective when looking at the true lifecycle cost of a water cooled data center. This study aims at addressing how one should evaluate the true total cost of ownership for water cooled data centers by considering the combined capital and operational cost for both the IT systems and the data center facility. It compares several metrics, including return-on-investment for three cooling technologies: traditional air cooling, rack-level cooling using rear door heat exchangers and direct water cooling via cold plates. The results highlight several important variables, namely, IT power, data center location, site electric utility cost, and construction costs and how each of these influence the total cost of ownership of water cooling. The study further looks at implementing water cooling as part of a new data center construction project versus a retrofit or upgrade into an existing data center facility.

Raised Floor Hybrid Cooled Data Center: Effect on Rack Inlet Air Temperatures When In Row Cooling Units are Installed Between the Racks

The heat dissipated by high performance IT equipment such as servers and switches in data centers is increasing rapidly, which makes the thermal management even more challenging. IT equipment is typically designed to operate at a rack inlet air temperature ranging between 10 °C and 35 °C. The newest published environmental standards for operating IT equipment proposed by ASHARE specify a long term recommended dry bulb IT air inlet temperature range as 18°C to 27°C. In terms of the short term specification, the largest allowable inlet temperature range to operate at is between 5°C and 45°C. Failure in maintaining these specifications will lead to significantly detrimental impacts to the performance and reliability of these electronic devices. Thus, understanding the cooling system is of paramount importance for the design and operation of data centers. In this paper, a hybrid cooling system is numerically modeled and investigated. The numerical modeling is conducted using a commercial computational fluid dynamics (CFD) code. The hybrid cooling strategy is specified by mounting the in row cooling units between the server racks to assist the raised floor air cooling. The effect of several input variables, including rack heat load and heat density, rack air flow rate, in row cooling unit operating cooling fluid flow rate and temperature, in row coil effectiveness, centralized cooling unit supply air flow rate, non-uniformity in rack heat load, and raised floor height are studied parametrically. Their detailed effects on the rack inlet air temperatures and the in row cooler performance are presented. The modeling results and corresponding analyses are used to develop general installation and operation guidance for the in row cooler strategy of a data center.