Thermomechanical behaviour of inverse diode in SiC MOSFETs under surge current stress

Author(s):  
S. Palanisamy ◽  
J. Lutz ◽  
R. Boldyrjew-Mast ◽  
T. Basler
Author(s):  
Xi Jiang ◽  
Jun Wang ◽  
Jianjun Chen ◽  
Zongjian Li ◽  
Dongyuan Zhai ◽  
...  
Keyword(s):  

2020 ◽  
Vol 1004 ◽  
pp. 814-821 ◽  
Author(s):  
Enea Bianda ◽  
Andrei Mihaila ◽  
Gianpaolo Romano ◽  
Lars Knoll ◽  
Stephan Wirths ◽  
...  

The aim of this study is to investigate the main contributing factors to the degradation of the intrinsic body diode in SiC MOSFETs, caused by the expansion of stacking faults (SFs) from the substrate into the epitaxial layer, and how it affects their performance. Additionally, a comparison between DC forward current stress and surge current pulse stress is shown.


2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.


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