scholarly journals Interconnection Networks for Scalable Quantum Computers

2006 ◽  
Author(s):  
N. Isailovic ◽  
Y. Patel ◽  
M. Whitney ◽  
J. Kubiatowicz
Keyword(s):  
Interconnection Networks ◽  
Quantum Computers

scholarly journals Interconnection Networks for Scalable Quantum Computers

2006 ◽  
Vol 34 (2) ◽  
pp. 366-377 ◽  
Author(s):  
Nemanja Isailovic ◽  
Yatish Patel ◽  
Mark Whitney ◽  
John Kubiatowicz
Keyword(s):  
Interconnection Networks ◽  
Quantum Computers

Quantum computers go for a spin

Nature ◽  
2005 ◽  
Author(s):  
Philip Ball
Keyword(s):  
Quantum Computers

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

The Essence of Quantum Computing

2018 ◽  
Author(s):  
Rajendra K. Bera
Keyword(s):  
Hilbert Space ◽  
Quantum Computing ◽  
Quantum Physics ◽  
Quantum Algorithms ◽  
Quantum Computers ◽  
Turing Machines ◽  
Classical Physics ◽  
Core Set ◽  
The World ◽  
Subordinate Role

It now appears that quantum computers are poised to enter the world of computing and establish its dominance, especially, in the cloud. Turing machines (classical computers) tied to the laws of classical physics will not vanish from our lives but begin to play a subordinate role to quantum computers tied to the enigmatic laws of quantum physics that deal with such non-intuitive phenomena as superposition, entanglement, collapse of the wave function, and teleportation, all occurring in Hilbert space. The aim of this 3-part paper is to introduce the readers to a core set of quantum algorithms based on the postulates of quantum mechanics, and reveal the amazing power of quantum computing.

Replication of Quantum Computing towards an Unconventional Environment using QuIDE

2019 ◽  
Vol 8 (4) ◽  
pp. 9461-9464
Keyword(s):  
Quantum Computer ◽  
Source Code ◽  
Circuit Diagram ◽  
Quantum Computers ◽  
Coordinated Development ◽  
Development Environment ◽  
Integrated Development ◽  
Complexity Of Algorithms ◽  
Performance Results ◽  
Exponential Complexity

Current quantum computer simulation strategies are inefficient in simulation and their realizations are also failed to minimize those impacts of the exponential complexity for simulated quantum computations. We proposed a Quantum computer simulator model in this paper which is a coordinated Development Environment – QuIDE (Quantum Integrated Development Environment) to support the improvement of algorithm for future quantum computers. The development environment provides the circuit diagram of graphical building and flexibility of source code. Analyze the complexity of algorithms shows the performance results of the simulator and used for simulation as well as result of its deployment during simulation

Quantitative Reliability Analysis of Redundant Multistage Interconnection Networks

1991 ◽  
Author(s):  
Nita M. Kini ◽  
Anup Kumar ◽  
Dharma P. Agrawal
Keyword(s):  
Reliability Analysis ◽  
Interconnection Networks ◽  
Multistage Interconnection Networks
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