High-speed high-precision analog rank order filter in CMOS technology

2004 ◽  
Author(s):  
R.G. Carvajal ◽  
J. Ramirez-Angulo ◽  
G.O. Ducoudray ◽  
A. Lopez-Martin
Keyword(s):  
High Precision ◽  
High Speed ◽  
Rank Order ◽  
Cmos Technology ◽  
Order Filter

High-speed high-precision CMOS analog rank order filter with O(n) complexity

2005 ◽  
Vol 40 (6) ◽  
pp. 1238-1248 ◽  
Author(s):  
R.G. Carvajal ◽  
J. Ramirez-Angulo ◽  
G.O. Ducoudray ◽  
A.J. Lopez-Martin
Keyword(s):  
High Precision ◽  
High Speed ◽  
Rank Order ◽  
Order Filter

scholarly journals Fast and Modular Analog Rank Order Filter Using CMOS Technology

2009 ◽  
Vol 55 (5) ◽  
pp. 201 ◽  
Author(s):  
R Mukund ◽  
AmitKumar Mishra
Keyword(s):  
Rank Order ◽  
Cmos Technology ◽  
Order Filter

High-speed high-precision min/max circuits in CMOS technology

2000 ◽  
Vol 36 (8) ◽  
pp. 697 ◽  
Author(s):  
R.G. Carvajal ◽  
J. Ramírez-Angulo ◽  
J. Martínez-Heredia
Keyword(s):  
High Precision ◽  
High Speed ◽  
Cmos Technology

scholarly journals DESIGN OF A HIGH-SPEED, RECONFIGURABLE, DIGITAL RANK ORDER FILTER

2010 ◽  
Vol 10 (1) ◽  
pp. 19-30
Author(s):  
George John Toscano ◽  
Pran K. Saha ◽  
A.H.M Zahirul Alam
Keyword(s):  
High Speed ◽  
Rank Order ◽  
Window Size ◽  
Binary Representation ◽  
Cmos Process ◽  
Clock Speed ◽  
Order Filter ◽  
Simulation Results ◽  
Hspice Simulation

A new architecture to realize a modular, high-speed, reconfigurable, digital Rank Order Filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed ROF. Using the proposed digital rank selection circuit it is possible to find the element of a certain rank in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. The size of the proposed ROF increases only linearly with the number of samples in each window to be ranked. The proposed ROF is also modular in nature, which means function of each part of the ROF is well defined and so the circuit can be easily expandable for larger window size. The proposed ROF has been implemented in FPGA and post-fit simulation results are presented in this paper. HSPICE simulation of the proposed ROF is also done for 0.18um CMOS process. The simulation result shows that the circuit could be operated at a clock speed of 500 MHz.

scholarly journals A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic

VLSI Design ◽  
2000 ◽  
Vol 11 (2) ◽  
pp. 115-128 ◽  
Author(s):  
İ. Hatirnaz ◽  
F. K. Gürkaynak ◽  
Y. Leblebici
Keyword(s):  
Word Length ◽  
High Speed ◽  
Rank Order ◽  
Window Size ◽  
Cmos Technology ◽  
Majority Voting ◽  
Threshold Logic ◽  
Scalable Architecture ◽  
Silicon Area ◽  
Median Filters

We present a new scalable architecture for the realization of fully programmable rank order filters (ROF). Capacitive Threshold Logic (CTL) gates are utilized for the implementation of the multi-input programmable majority (voting) functions required in the architecture. The CTL-based realization of the majority gates used in the ROF architecture allows the filter rank as well as the window size to be user-programmable, using a much smaller silicon area, compared to conventional realizations of digital median filters. The proposed filter architecture is completely modular and scalable, and the circuit complexity grows only linearly with maximum window size (m) and with word length (n). A prototype of the proposed filter circuit has been designed and fabricated using double-polysilicon 0.8 μm CMOS technology. Detailed post-layout simulations and test results of the ROF prototype circuit indicate that the new architecture can accommodate sampling clock rates of up to 50 MHz, corresponding to an effective data processing rate of 800 Mb/s for a very large filter with window size 63 and word length of 16 bits.

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