A new VLSI architecture for a reconfigurable, high-speed, digital Rank Order Filter

2008 ◽  
Author(s):  
George J. Toscano ◽  
Pran K. Saha ◽  
A.H.M. Zahirul Alam
Keyword(s):  
High Speed ◽  
Rank Order ◽  
Vlsi Architecture ◽  
Order Filter

High-speed high-precision CMOS analog rank order filter with O(n) complexity

2005 ◽  
Vol 40 (6) ◽  
pp. 1238-1248 ◽  
Author(s):  
R.G. Carvajal ◽  
J. Ramirez-Angulo ◽  
G.O. Ducoudray ◽  
A.J. Lopez-Martin
Keyword(s):  
High Precision ◽  
High Speed ◽  
Rank Order ◽  
Order Filter

scholarly journals DESIGN OF A HIGH-SPEED, RECONFIGURABLE, DIGITAL RANK ORDER FILTER

2010 ◽  
Vol 10 (1) ◽  
pp. 19-30
Author(s):  
George John Toscano ◽  
Pran K. Saha ◽  
A.H.M Zahirul Alam
Keyword(s):  
High Speed ◽  
Rank Order ◽  
Window Size ◽  
Binary Representation ◽  
Cmos Process ◽  
Clock Speed ◽  
Order Filter ◽  
Simulation Results ◽  
Hspice Simulation

A new architecture to realize a modular, high-speed, reconfigurable, digital Rank Order Filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed ROF. Using the proposed digital rank selection circuit it is possible to find the element of a certain rank in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. The size of the proposed ROF increases only linearly with the number of samples in each window to be ranked. The proposed ROF is also modular in nature, which means function of each part of the ROF is well defined and so the circuit can be easily expandable for larger window size. The proposed ROF has been implemented in FPGA and post-fit simulation results are presented in this paper. HSPICE simulation of the proposed ROF is also done for 0.18um CMOS process. The simulation result shows that the circuit could be operated at a clock speed of 500 MHz.

scholarly journals VLSI ARCHITECTURE OF PARALLEL MULTIPLIER– ACCUMULATOR BASED ON RADIX-2 MODIFIED BOOTH ALGORITHM

2012 ◽  
pp. 40-46
Author(s):  
Mr.M.V. Sathish ◽  
Mrs. Sailaja
Keyword(s):  
Signal Processing ◽  
High Speed ◽  
High Performance ◽  
Vlsi Architecture ◽  
Clock Frequency ◽  
Parallel Multiplier ◽  
Hybrid Type ◽  
Standard Design ◽  
Overall Performance ◽  
And Performance

A new architecture of multiplier-andaccumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposing method CSA tree uses 1’s-complement-based radix-2 modified Booth’s algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

Sign in / Sign up

Export Citation Format

Share Document