scholarly journals DESIGN OF A HIGH-SPEED, RECONFIGURABLE, DIGITAL RANK ORDER FILTER

2010 ◽  
Vol 10 (1) ◽  
pp. 19-30
Author(s):  
George John Toscano ◽  
Pran K. Saha ◽  
A.H.M Zahirul Alam
Keyword(s):  
High Speed ◽  
Rank Order ◽  
Window Size ◽  
Binary Representation ◽  
Cmos Process ◽  
Clock Speed ◽  
Order Filter ◽  
Simulation Results ◽  
Hspice Simulation

A new architecture to realize a modular, high-speed, reconfigurable, digital Rank Order Filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed ROF. Using the proposed digital rank selection circuit it is possible to find the element of a certain rank in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. The size of the proposed ROF increases only linearly with the number of samples in each window to be ranked. The proposed ROF is also modular in nature, which means function of each part of the ROF is well defined and so the circuit can be easily expandable for larger window size. The proposed ROF has been implemented in FPGA and post-fit simulation results are presented in this paper. HSPICE simulation of the proposed ROF is also done for 0.18um CMOS process. The simulation result shows that the circuit could be operated at a clock speed of 500 MHz.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 257-269
Author(s):  
Vimukth John ◽  
Shylu Sam ◽  
S. Radha ◽  
P. Sam Paul ◽  
Joel Samuel
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Arithmetic Function ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Content Type ◽  
Simulation Results ◽  
Circuit Power ◽  
Or Gate

Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

scholarly journals A High-Speed and Low-Offset Dynamic Latch Comparator

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Labonnah Farzana Rahman ◽  
Mamun Bin Ibne Reaz ◽  
Chia Chieu Yin ◽  
Mohammad Marufuzzaman ◽  
Mohammad Anisur Rahman
Keyword(s):  
Monte Carlo Simulation ◽  
Monte Carlo ◽  
Power Dissipation ◽  
High Speed ◽  
Cmos Process ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Simulation Results ◽  
Low Offset

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of148.80 μm×59.70 μm.

scholarly journals 10-GHz wide tuning-range linear voltage-controlled oscillator

2021 ◽  
Author(s):  
Sameh Soliman
Keyword(s):  
High Speed ◽  
Tuning Range ◽  
Serial Communication ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Center Frequency ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Communication Circuits ◽  
Simulation Results

The current high-growth nature of digital communications demands higher speed serial communication circuits. Present day technologies barely manage to keep up with this demand, and new techniques are required to ensure that serial communication can continnue to expand and grow. The goal of this work is to optimize the performance of an essential building block of serial communication circuits, namely, the phase-locked loop (PLL), so that it can cope with today's high-speed communication. Due to its popularity, the optimization has targeted the charge-pump-based implementqation of the phase-locked loop. This goal is achieved by researching, designing, and evaluating high speed serial communication circuits. Research has involved an in-depth study of the state of the art in high-speed serial communication circuits ; high-speed, controlled oscillators, and CMOS technology. An LC, voltage-controlled oscillator (VCO) is designed in 0.18-micron, mixed-signal, 6-metal-2-poly, CMOS process. A novel tuning technique is employed to tune its output frequency. Simulation results shows that it provides quadrature and differential outputs, operates with 10 GHz center frequency, 600-MHz tuning range centered around its center frequency, and phase noise of -95 dBc/Hz at 1-MHz offset from the fundamental harmonic of its output, and draws 10 ,A of DC current from a single 1.8-V power supply. Also, it exhibits a good linearity throughout its tuning range. The new tuning technique increases the tuning range of the VCO to 6% of its center frequency compared to the 1-to-2% typical value. As its locking performance depends on the characteristic of the employed VCO and to demonstrate the effect of optimizing the tuning range of the VCO, a charge-pump PLL is designed. Simulation results shows that the PLL acquisition range is 300 MHz compared to a maximum value of 100 MHz when a conventional LC VCO is employed. Also, as a measure of its tracking range, the maximum frequency slew rate of its input has improved by 40%.

HIGH SPEED HIGH PRECISION VOLTAGE-MODE MAX AND MIN CIRCUITS

2007 ◽  
Vol 16 (02) ◽  
pp. 233-244 ◽  
Author(s):  
SARANG KAZEMI NIA ◽  
ABDOLLAH KHOEI ◽  
KHEIROLLAH HADIDI
Keyword(s):  
High Precision ◽  
High Speed ◽  
Voltage Mode ◽  
Precision Voltage ◽  
Simple Expansion ◽  
Differential Pair ◽  
Simulation Results ◽  
Hspice Simulation

This paper presents a new high speed voltage-mode MAX–MIN method for fuzzy applications. In the proposed circuits, a differential pair is employed to choose the desired input. In addition to high speed, high precision and simple expansion for multiple inputs are the main advantages of this method. HSPICE simulation results show that the proposed circuit has maximum of 1% error at 100 MHz.

scholarly journals 10-GHz wide tuning-range linear voltage-controlled oscillator

2021 ◽  
Author(s):  
Sameh Soliman
Keyword(s):  
High Speed ◽  
Tuning Range ◽  
Serial Communication ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Center Frequency ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Communication Circuits ◽  
Simulation Results

The current high-growth nature of digital communications demands higher speed serial communication circuits. Present day technologies barely manage to keep up with this demand, and new techniques are required to ensure that serial communication can continnue to expand and grow. The goal of this work is to optimize the performance of an essential building block of serial communication circuits, namely, the phase-locked loop (PLL), so that it can cope with today's high-speed communication. Due to its popularity, the optimization has targeted the charge-pump-based implementqation of the phase-locked loop. This goal is achieved by researching, designing, and evaluating high speed serial communication circuits. Research has involved an in-depth study of the state of the art in high-speed serial communication circuits ; high-speed, controlled oscillators, and CMOS technology. An LC, voltage-controlled oscillator (VCO) is designed in 0.18-micron, mixed-signal, 6-metal-2-poly, CMOS process. A novel tuning technique is employed to tune its output frequency. Simulation results shows that it provides quadrature and differential outputs, operates with 10 GHz center frequency, 600-MHz tuning range centered around its center frequency, and phase noise of -95 dBc/Hz at 1-MHz offset from the fundamental harmonic of its output, and draws 10 ,A of DC current from a single 1.8-V power supply. Also, it exhibits a good linearity throughout its tuning range. The new tuning technique increases the tuning range of the VCO to 6% of its center frequency compared to the 1-to-2% typical value. As its locking performance depends on the characteristic of the employed VCO and to demonstrate the effect of optimizing the tuning range of the VCO, a charge-pump PLL is designed. Simulation results shows that the PLL acquisition range is 300 MHz compared to a maximum value of 100 MHz when a conventional LC VCO is employed. Also, as a measure of its tracking range, the maximum frequency slew rate of its input has improved by 40%.

High-speed high-precision CMOS analog rank order filter with O(n) complexity

2005 ◽  
Vol 40 (6) ◽  
pp. 1238-1248 ◽  
Author(s):  
R.G. Carvajal ◽  
J. Ramirez-Angulo ◽  
G.O. Ducoudray ◽  
A.J. Lopez-Martin
Keyword(s):  
High Precision ◽  
High Speed ◽  
Rank Order ◽  
Order Filter
Sign in / Sign up

Export Citation Format

Share Document