Behavioral modeling of current conveyors for circuit simulation

Behavior models are proposed for HSPICE simulation of first-, second- and third-generation current conveyors. They can be used to speed up the exploration and verification of current conveyor-based circuit designs. To demonstrate the feasibility and workability of the proposed HSPICE simulation models, they are used as the current measuring devices for grounded and floating current sensing, and the simulation results are consistent with the theoretical expectation. The flexibility in the current sensing capability of the CCIII is also shown by a practical example using the behavior model. HSPICE simulation results are given.

A Transformation Methodology of Normal Nonlinear Resistors/Conductors to Inverses

This work proposes a simple transformation methodology of normal nonlinear resistors/conductors to their inverted topologies in their floating and grounded versions (NNR/C). It is demonstrated that inverted topologies can also be configured as incremental or decremental nonlinear resistors/conductors. The main fingerprints of an NNR/C are holding up after the transformation and it is demonstrated that an inverse nonlinear resistor/conductor becomes a linear resistor/conductor when the operating frequency of the signal source decreases, inverse behavior in comparison with one memristor. Illustrative examples are given for floating and grounded nonlinear resistors and in both configurations. HSPICE simulation results are provided confirming the theory. Moreover, the normal and inverses resistors can be reconfigured in order to be used in future applications such as programmable analog circuits.

Design of bootstrap integrated synchronous rectifier

Based on the research of the development of synchronous rectification technology, this paper proposes a circuit structure of bootstrap synchronous rectifier chip. Firstly, through the research of synchronous rectification technology, the architecture of synchronous rectification chip is determined. After the system design is completed, the internal units of the chip are designed in blocks under the 0.35 μm BCD process, and the specific circuit design is completed. Each unit has been verified by HSPICE simulation and has reached the specified index. The system constructed by this has also been verified by simulation, and the simulation results are consistent with the expected results, indicating that the main design functions of the circuit have been realized.

A Modified Signal Feed-Through Pulsed Flip- Flop for Low Power Applications

In this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.

Design of Dynamic Binary Circuits Based on Floating-Gate Technology

The dynamic circuit technology can decrease the whole power consumption, and the Floating-gate technology can simplify the circuit structure, which will also decrease the area and power consumption of IC. Taking the advantages of both ,we propose a new dynamic binary circuit based on floating-gate technology. The HSPICE simulation results using TSMC 0.35μm double-polysilicon CMOS technology validate the correctness of the proposed approach, and the proposed circuits also have considerable simpler structures.

BiCMOS Flip-Flop Design Based on NPN-NPN Feedback Driver Circuits

based on the analyzing the characteristic of BiCMOS circuits and theory of transmission voltage-switches, we proposed a general structure of binary BiCMOS circuit based on NPN-NPN feedback driver circuit. Then we designed binary BiCMOS master-slave JK flip-flop circuit and transmission gate D flip-flop circuit base on the general structure of NPN-NPN feedback driver circuit. With using HSPICE simulation, the results show that the circuits have the correct logical function. The proposed driver circuits can be used in the design of BiCMOS sequential circuits.

A NEW ROBUST AND HIGH-PERFORMANCE HYBRID FULL ADDER CELL

A new 1-bit hybrid Full Adder cell is presented in this paper with the aim of reaching a robust and high-performance adder structure. While most of recent Full Adders are proposed with the purpose of using fewer transistors, they suffer from some disadvantages such as output or internal non-full-swing nodes and poor driving capability. Considering these drawbacks, they might not be a good choice to operate in a practical environment. Lowering the number of transistors can inherently lead to smaller occupied area, higher speed and lower power consumption. However, other parameters, such as robustness to PVT variations and rail-to-rail operation, should also be considered. While the robustness is taken into account, HSPICE simulation demonstrates a great improvement in terms of speed and power-delay product (PDP).

DESIGN OF A HIGH-SPEED, RECONFIGURABLE, DIGITAL RANK ORDER FILTER

A new architecture to realize a modular, high-speed, reconfigurable, digital Rank Order Filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed ROF. Using the proposed digital rank selection circuit it is possible to find the element of a certain rank in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. The size of the proposed ROF increases only linearly with the number of samples in each window to be ranked. The proposed ROF is also modular in nature, which means function of each part of the ROF is well defined and so the circuit can be easily expandable for larger window size. The proposed ROF has been implemented in FPGA and post-fit simulation results are presented in this paper. HSPICE simulation of the proposed ROF is also done for 0.18um CMOS process. The simulation result shows that the circuit could be operated at a clock speed of 500 MHz.

Design of an Organic Pixel Addressing Circuit for Active-Matrix OLED Displays

In this paper, we present a new model for an organic pixel addressing circuit based on four-transistor configuration. The proposed circuit doesn’t have the problems of regular configurations which are based on four-thin film transistors (TFT). Circuits based on four-TFT have many advantages, but the only problem is the existence of current peaks at the beginning of each pixel luminescence. Both 4-TFT based configuration and proposed one were simulated using HSPICE. Simulation results indicate the superiority of the proposed method compared with existing technique.

HIGH SPEED HIGH PRECISION VOLTAGE-MODE MAX AND MIN CIRCUITS

This paper presents a new high speed voltage-mode MAX–MIN method for fuzzy applications. In the proposed circuits, a differential pair is employed to choose the desired input. In addition to high speed, high precision and simple expansion for multiple inputs are the main advantages of this method. HSPICE simulation results show that the proposed circuit has maximum of 1% error at 100 MHz.