An Adaptively Biased LDO Regulator with 11nA Quiescent Current and 50mA Available Load

2021 ◽  
Author(s):  
Jing Li ◽  
Jiping Li ◽  
Jianyu Zhang ◽  
Yu He ◽  
Qiuzhen Xu ◽  
...  
Keyword(s):  
Quiescent Current ◽  
Ldo Regulator

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

Integration ◽  
2014 ◽  
Vol 47 (2) ◽  
pp. 204-212 ◽  
Author(s):  
Rasoul Fathipour ◽  
Alireza Saberkari ◽  
Herminio Martinez ◽  
Eduard Alarcón
Keyword(s):  
Current Mode ◽  
Slew Rate ◽  
Current Output ◽  
Error Amplifier ◽  
Quiescent Current ◽  
Ldo Regulator

Design of an Output-Capacitorless LDO Regulator with Adaptive Power Transistors

2014 ◽  
Vol 631-632 ◽  
pp. 322-326
Author(s):  
Shang Sheng Chi ◽  
Wei Hu ◽  
Yu Sen Xu ◽  
Ming Hui Fan
Keyword(s):  
Load Condition ◽  
Absolute Temperature ◽  
Bandgap Reference ◽  
Load Current ◽  
Power Transistors ◽  
Light Load ◽  
Reference Circuit ◽  
Quiescent Current ◽  
Adaptive Power ◽  
Ldo Regulator

This paper presents a bandgap reference and an output-capacitorless LDO regulator with adaptive power transistors. The bandgap reference consists of a current reference circuit, a bipolar transistor and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed LDO improves load transient and light load efficiency by permitting the regulator to transform itself between 2-stage and 3-stage topologies, depending on the load current condition. Cadence simulation with SMIC 0.18 μm process shows that the bandgap reference generates a reference voltage 569 mV and the quiescent current is only 0.23 μA, the proposed LDO generates an output voltage 1 V, the quiescent current is 0.88 μA (including bandgap reference) at no-load condition, the undershoot /overshoot voltage is 187 mV/152 mV and the settling time is 5 μs as load current suddenly changes from 0 to 100 mA, or vice versa.

Sign in / Sign up

Export Citation Format

Share Document