High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

Integration ◽  
2014 ◽  
Vol 47 (2) ◽  
pp. 204-212 ◽  
Author(s):  
Rasoul Fathipour ◽  
Alireza Saberkari ◽  
Herminio Martinez ◽  
Eduard Alarcón
2014 ◽  
Vol 50 (10) ◽  
pp. 771-773 ◽  
Author(s):  
Han‐Xiao Du ◽  
Xin‐Quan Lai ◽  
Cong Liu ◽  
Yuan Chi

2011 ◽  
Vol 20 (07) ◽  
pp. 1277-1286 ◽  
Author(s):  
MERIH YILDIZ ◽  
SHAHRAM MINAEI ◽  
EMRE ARSLAN

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.


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