scholarly journals Low quiescent current capacitor-less LDO regulator with high slew rate super class AB CMOS OTA

2020 ◽  
Vol 1550 ◽  
pp. 052022
Author(s):  
Peng Ni ◽  
Shengming Huang ◽  
Quanzhen Duan
Integration ◽  
2014 ◽  
Vol 47 (2) ◽  
pp. 204-212 ◽  
Author(s):  
Rasoul Fathipour ◽  
Alireza Saberkari ◽  
Herminio Martinez ◽  
Eduard Alarcón

2021 ◽  
Vol 11 (3) ◽  
pp. 31
Author(s):  
Anindita Paul ◽  
Mario Renteria-Pinon ◽  
Jaime Ramirez-Angulo ◽  
Ricardo Bolaños-Pérez ◽  
Héctor Vázquez-Leal ◽  
...  

An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents can be much higher than the total op-amp quiescent current. The enhanced performance is achieved by utilizing a simple low-power auxiliary amplifier with resistive local common-mode feedback that increases the quiescent power dissipation by less than 10%. The proposed class AB op-amp is characterized by significantly enhanced large-signal dynamic, static current efficiency, and small-signal figures of merits. The dynamic current efficiency is 15.6 higher, the static current efficiency is 8.9 times higher, and the small-signal figure of merit is 2.3 times higher than the conventional class-A op-amp. A global figure of merit that determines an op-amp’s ultimate speed is 6.33 times higher than the conventional class A op-amp.


2011 ◽  
Vol 20 (07) ◽  
pp. 1277-1286 ◽  
Author(s):  
MERIH YILDIZ ◽  
SHAHRAM MINAEI ◽  
EMRE ARSLAN

This work presents a high-slew rate rail-to-rail buffer amplifier, which can be used for flat panel displays. The proposed buffer amplifier is composed of two transconductance amplifiers, two current comparators and a push-pull output stage. Phase compensation technique is also used to improve the phase margin value of the proposed buffer amplifier for different load capacitances. Post-layout simulations of the proposed buffer amplifier are performed using 0.35 μm AMS CMOS process parameters and 3.3 V power supply. The circuit is tested under a 600 pF capacitive load. An average settling time of 0.85 μs under a full voltage swing is obtained, while only 3 μA quiescent current is drawn from the power supply. Monte Carlo analysis is also added to show the process variation effects on the circuit.


Author(s):  
Antonio J. Lopez-Martin ◽  
Jose Algueta ◽  
Lucia Acosta ◽  
Ramon G. Carvajal ◽  
Jaime Ramirez-Angulo

2016 ◽  
Vol 90 (1) ◽  
pp. 227-235 ◽  
Author(s):  
Jaejin Yeo ◽  
Khurram Javed ◽  
Jaeseong Lee ◽  
Jeongjin Roh ◽  
Jae-Do Park

Author(s):  
Kunchala Sivakumari ◽  
Avireni Srinivasulu ◽  
V. Venkata Reddy
Keyword(s):  

Sign in / Sign up

Export Citation Format

Share Document