A Capacitorless LDO Regulator With Fast Feedback Technique and Low-Quiescent Current Error Amplifier

2013 ◽  
Vol 60 (6) ◽  
pp. 326-330 ◽  
Author(s):  
Young-il Kim ◽  
Sang-sun Lee
Keyword(s):  
Error Amplifier ◽  
Quiescent Current ◽  
Current Error ◽  
Ldo Regulator

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

Integration ◽  
2014 ◽  
Vol 47 (2) ◽  
pp. 204-212 ◽  
Author(s):  
Rasoul Fathipour ◽  
Alireza Saberkari ◽  
Herminio Martinez ◽  
Eduard Alarcón
Keyword(s):  
Current Mode ◽  
Slew Rate ◽  
Current Output ◽  
Error Amplifier ◽  
Quiescent Current ◽  
Ldo Regulator

Low quiescent current linear regulator using combination structure of bandgap and error amplifier

2014 ◽  
Vol 50 (10) ◽  
pp. 771-773 ◽  
Author(s):  
Han‐Xiao Du ◽  
Xin‐Quan Lai ◽  
Cong Liu ◽  
Yuan Chi
Keyword(s):  
Error Amplifier ◽  
Linear Regulator ◽  
Quiescent Current

scholarly journals A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2108
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Fully Integrated ◽  
Low Voltage Operation ◽  
Error Amplifier ◽  
Ldo Regulator

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

scholarly journals DESIGN OF ONCHIP LOW DROPOUT (LDO) REGULATOR FOR POWER MANAGEMENT APPLICATION

2017 ◽  
Vol 10 (13) ◽  
pp. 1
Author(s):  
Apratim Chatterjee ◽  
Manikandan P
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Transient Response ◽  
Advantages And Disadvantages ◽  
Error Amplifier ◽  
Linear Characteristic ◽  
Management Application ◽  
Input Range ◽  
Low Dropout Regulator ◽  
Ldo Regulator

A low dropout regulator is proposed in this paper. The regulator is designed with classic five pack model to decrease the number of devices and make the design compact and also reduce the power consumption. The system is designed and simulated in cadence virtuoso environment under 180nm technology node. Three models of LDO is proposed in this paper, with all having same error amplifier but with small variations. The advantages and disadvantages of each model will be discussed in the paper. The LDOs have linear characteristic over a good input range. It has good transient response to load variation. 

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