Background Calibration in Pipelined SAR ADCs Exploiting PVT-Tracking Metastability Detector

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401732 ◽

2021 ◽

Author(s):

Lizhen Zhang ◽

Jianhui Wu

Keyword(s):

Background Calibration

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Digital Background Calibration for a 14-bit 100-MS/s Pipelined ADC Using Signal-Dependent Dithering

IEICE Transactions on Electronics ◽

10.1587/transele.e97.c.207 ◽

2014 ◽

Vol E97.C (3) ◽

pp. 207-214

Author(s):

Zhao-xin XIONG ◽

Min CAI ◽

Xiao-Yong HE ◽

Yun YANG

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

Digital Background Calibration

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Digital architecture for background calibration of pipeline ADCs

5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications ◽

10.1049/cp:20050171 ◽

2005 ◽

Author(s):

A. Delic-Ibukic

Keyword(s):

Background Calibration ◽

Digital Architecture ◽

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An ICA Framework for Digital Background Calibration of Analog-to-Digital Converters

Sampling Theory, Signal Processing, and Data Analysis ◽

10.1007/bf03549557 ◽

2012 ◽

Vol 11 (2-3) ◽

pp. 253-270

Author(s):

Yun Chiu ◽

Seung-Chul Lee ◽

Wenbo Liu

Keyword(s):

Analog To Digital Converters ◽

Background Calibration ◽

Analog To Digital ◽

Digital Background Calibration

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A current-mode stimulator circuit with two-step charge balancing background calibration

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) ◽

10.1109/iscas.2013.6571867 ◽

2013 ◽

Author(s):

Anh Tuan Do ◽

Yung Sern Tan ◽

Gordon M. Xiong ◽

Cleo Choong ◽

Zhi Hui Kong ◽

...

Keyword(s):

Current Mode ◽

Background Calibration ◽

Charge Balancing ◽

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A 1GS/s 10bit SAR ADC with background calibration in 28nm CMOS

Microelectronics Journal ◽

10.1016/j.mejo.2021.105120 ◽

2021 ◽

pp. 105120

Author(s):

Zheng Qiu ◽

Yudong Ouyang ◽

Lijie Yang ◽

Liqi Sun

Keyword(s):

Sar Adc ◽

Background Calibration

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A 4.1mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process

2016 International SoC Design Conference (ISOCC) ◽

10.1109/isocc.2016.7799740 ◽

2016 ◽

Author(s):

Esther Kim ◽

Deokgwan Jeong ◽

Taehyoun Oh

Keyword(s):

Cmos Process ◽

Background Calibration

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Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure

2010 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2010.5774756 ◽

2010 ◽

Author(s):

Takuya Yagi ◽

Kunihiko Usui ◽

Tatsuji Matsuura ◽

Satoshi Uemori ◽

Yohei Tan ◽

...

Keyword(s):

Open Loop ◽

Pipelined Adc ◽

Background Calibration ◽

Calibration Algorithm ◽

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A fully digital background calibration of timing skew in undersampling TI-ADC

2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS) ◽

10.1109/newcas.2014.6933983 ◽

2014 ◽

Author(s):

Han Le Duc ◽

Chadi Jabbour ◽

Patricia Desgreys ◽

Olivier Jamin ◽

Nguyen Van Tam

Keyword(s):

Background Calibration ◽

Digital Background Calibration ◽

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A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration

10.1109/a-sscc53895.2021.9634827 ◽

2021 ◽

Author(s):

Chun-Yu Lin ◽

Yu-Wei Huang ◽

Tsung-Hsien Lin

Keyword(s):

Background Calibration ◽

Clock Generator

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A Deterministic Background Calibration Technique for Voltage Controlled Oscillator Based ADC

High-Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing ◽

10.1007/978-3-319-07938-7_16 ◽

2014 ◽

pp. 361-377

Author(s):

Sachin Rao ◽

Pavan Kumar Hanumolu

Keyword(s):

Voltage Controlled Oscillator ◽

Background Calibration ◽

Calibration Technique

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