A ± 20-ppm -50°C-105°C 1-µA 32.768-kHz Clock Generator with a System-HFXO-Assisted Background Calibration

Mapping Intimacies ◽

10.1109/a-sscc53895.2021.9634827 ◽

2021 ◽

Author(s):

Chun-Yu Lin ◽

Yu-Wei Huang ◽

Tsung-Hsien Lin

Keyword(s):

Background Calibration ◽

Clock Generator

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A 25 MHz crystal less clock generator with background calibration against process and temperature variation

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2016.04.007 ◽

2016 ◽

Vol 52 ◽

pp. 28-37 ◽

Author(s):

Wei-Bin Yang ◽

Ming-Hao Hong

Keyword(s):

Temperature Variation ◽

Background Calibration ◽

Clock Generator

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Digital Background Calibration for a 14-bit 100-MS/s Pipelined ADC Using Signal-Dependent Dithering

IEICE Transactions on Electronics ◽

10.1587/transele.e97.c.207 ◽

2014 ◽

Vol E97.C (3) ◽

pp. 207-214

Author(s):

Zhao-xin XIONG ◽

Min CAI ◽

Xiao-Yong HE ◽

Yun YANG

Keyword(s):

Pipelined Adc ◽

Background Calibration ◽

Digital Background Calibration

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Digital architecture for background calibration of pipeline ADCs

5th IEE International Conference on ADDA 2005. Advanced A/D and D/A Conversion Techniques and their Applications ◽

10.1049/cp:20050171 ◽

2005 ◽

Author(s):

A. Delic-Ibukic

Keyword(s):

Background Calibration ◽

Digital Architecture ◽

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Low-skew clock generator with dynamic impedance and delay matching

1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278) ◽

10.1109/isscc.1999.759183 ◽

2003 ◽

Author(s):

A. Balatsos ◽

D. Lewis

Keyword(s):

Clock Generator ◽

Dynamic Impedance

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An ICA Framework for Digital Background Calibration of Analog-to-Digital Converters

Sampling Theory, Signal Processing, and Data Analysis ◽

10.1007/bf03549557 ◽

2012 ◽

Vol 11 (2-3) ◽

pp. 253-270

Author(s):

Yun Chiu ◽

Seung-Chul Lee ◽

Wenbo Liu

Keyword(s):

Analog To Digital Converters ◽

Background Calibration ◽

Analog To Digital ◽

Digital Background Calibration

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A spread spectrum clock generator with a wide frequency and attenuation tuning range based on a third-order error-feedback delta-sigma modulator

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-009-9428-1 ◽

2009 ◽

Vol 65 (1) ◽

pp. 115-121

Author(s):

Jia Peng Zheng ◽

Ruth Wei Li ◽

Peng Ren ◽

Yi Yang ◽

Chien Chun Shao ◽

...

Keyword(s):

Spread Spectrum ◽

Tuning Range ◽

Clock Generator ◽

Error Feedback ◽

Third Order ◽

Order Error ◽

Delta Sigma Modulator ◽

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A current-mode stimulator circuit with two-step charge balancing background calibration

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) ◽

10.1109/iscas.2013.6571867 ◽

2013 ◽

Author(s):

Anh Tuan Do ◽

Yung Sern Tan ◽

Gordon M. Xiong ◽

Cleo Choong ◽

Zhi Hui Kong ◽

...

Keyword(s):

Current Mode ◽

Background Calibration ◽

Charge Balancing ◽

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R, G, B acquisition interface with line-locked clock generator for flat panel display

IEEE Journal of Solid-State Circuits ◽

10.1109/4.701244 ◽

1998 ◽

Vol 33 (7) ◽

pp. 1009-1013 ◽

Author(s):

H. Marie ◽

P. Belin

Keyword(s):

Clock Generator ◽

Flat Panel Display ◽

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A Charge Pump Circuit --- Cascading High-Voltage Clock Generator

4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008) ◽

10.1109/delta.2008.94 ◽

2008 ◽

Author(s):

Wen Chang Huang ◽

Jin Chang Cheng ◽

Po Chih Liou

Keyword(s):

High Voltage ◽

Charge Pump ◽

Clock Generator ◽

A Charge ◽

Charge Pump Circuit

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Design of a low phase error multiphase clock generator for modern wideband receivers

2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME) ◽

10.1109/prime.2016.7519504 ◽

2016 ◽

Author(s):

Miguel D. Fernandes ◽

Luis B. Oliveira ◽

Joao Goes ◽

Joao P. Oliveira

Keyword(s):

Phase Error ◽

Clock Generator

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