A 4.1mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process

2016 ◽  
Author(s):  
Esther Kim ◽  
Deokgwan Jeong ◽  
Taehyoun Oh
Keyword(s):  
Duty Cycle ◽  
Cmos Process ◽  
Background Calibration

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

scholarly journals Duty-Cycled Wireless Power Transmission for Millimeter-Sized Biomedical Implants

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2130
Author(s):  
Muhammad Abrar Akram ◽  
Kai-Wen Yang ◽  
Sohmyung Ha
Keyword(s):  
Duty Cycle ◽  
Power Transmission ◽  
Electromagnetic Coupling ◽  
System Level ◽  
Cmos Process ◽  
Biomedical Implants ◽  
Wireless Power ◽  
Wireless Power Transmission ◽  
Short Period ◽  
Circuit Components

Wireless power transmission (WPT) using an inductively coupled link is one of the most popular approaches to deliver power wirelessly to biomedical implants. As the electromagnetic wave travels through the tissue, it is attenuated and absorbed by the tissue, resulting in much weaker electromagnetic coupling than in the air. As a result, the received input power on the implant is very weak, and so is the input voltage at the rectifier, which is the first block that receives the power on the implant. With such a small voltage amplitude, the rectifier inevitably has a very poor power conversion efficiency (PCE), leading to a poor power transfer efficiency (PTE) of the overall WPT system. To address this challenge, we propose a new system-level WPT method based on duty cycling of the power transmission for millimeter-scale implants. In the proposed method, the power transmitter (TX) transmits the wave with a duty cycle. It transmits only during a short period of time and pauses for a while instead of transmitting the wave continuously. In doing so, the TX power during the active period can be increased while preserving the average TX power and the specific absorption rate (SAR). Then, the incoming voltage becomes significantly larger at the rectifier, so the rectifier can rectify the input with a higher PCE, leading to improved PTE. To investigate the design challenges and applicability of the proposed duty-cycled WPT method, a case for powering a 1 × 1-mm2-sized neural implant through the skull is constructed. The implant, a TX, and the associated environment are modeled in High-Frequency Structure Simulator (HFSS), and the circuit simulations are conducted in Cadence with circuit components in a 180-nm CMOS process. At a load resistor of 100 kΩ, an output capacitor of 4 nF, and a carrier frequency of 144 MHz, the rectifier’s DC output voltage and PCE are increased by 300% (from 1.5 V to 6 V) and by 50% (from 14% to 64%), respectively, when the duty cycle ratio of the proposed duty-cycled power transmission is varied from 100% to 5%.

A Stable Mode-Selectable Oscillator with Variable Duty Cycle and High-Efficiency

2015 ◽  
Vol 24 (09) ◽  
pp. 1550132 ◽  
Author(s):  
Li-Ye Cheng ◽  
Xin-Quan Lai
Keyword(s):  
Duty Cycle ◽  
High Efficiency ◽  
Dynamic Performance ◽  
Operation Mode ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Process ◽  
Pump Efficiency ◽  
Stable Mode ◽  
Wide Range

A mode-selectable oscillator (OSC) with variable duty cycle for improved charge pump efficiency is proposed in this paper. The novel OSC adjusts its duty cycle according to the operation mode of the charge pump, thus improves the charge-pump efficiency and dynamic performance. The control of variable duty cycle is implemented in digital logic hence it provides robust noise immunity and instantaneous response. The OSC and the charge-pump have been implemented in a 0.6-μm 40-V CMOS process. Experimental results show that the peak efficiency is 92.7% at 200-mA load, the recovery time is less than 25 μs and load transient is 15 mV under 500-mA load variation. The system is able to work under a wide range of input voltage (V IN ) in all modes with low EMI.

scholarly journals A 6-Locking Cycles All-Digital Duty Cycle Corrector with Synchronous Input Clock

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 860
Author(s):  
Shao-Ku Kao
Keyword(s):  
Duty Cycle ◽  
Delay Line ◽  
Supply Voltage ◽  
Cmos Process ◽  
Delay Lines ◽  
Clock Frequency ◽  
Quantization Method ◽  
Total Delay ◽  
Chip Area ◽  
Measurement Results

This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm2, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.

Analog-Based CMOS Duty Cycle Corrector with 50–800 MHz Operating Range

2015 ◽  
Vol 24 (07) ◽  
pp. 1550100
Author(s):  
Rui Ma ◽  
Zhangming Zhu ◽  
Maliang Liu ◽  
Ping Gan ◽  
Yintang Yang
Keyword(s):  
High Resolution ◽  
Duty Cycle ◽  
High Speed ◽  
Delay Line ◽  
Cmos Process ◽  
Input Frequency ◽  
Frequency Range ◽  
Locking Range ◽  
Layout Area ◽  
Forward Body Bias

In this paper, a novel accurate analog-based 50% duty cycle corrector (DCC) for high-speed and high-resolution operations is presented. Due to the performance limitations of conventional DCCs, such as a confined locking range and overtone locking, a novel delay line using forward-body-bias technique and reset circuit are adopted to enlarge the locking range of the proposed DCC. Simulated results based on the standard 0.18 μm 1.8 V standard CMOS process show that output duty cycle error is less than ±1% over an input frequency range of 50–800 MHz. The peak-to-peak jitter at 800 MHz is 789.77 fs with a power consumption of 11.09 mW. The active layout area of the proposed DCC is 0.21 × 0.21 mm2.

A Design of High Frequency Clock Generation Circuit

2013 ◽  
Vol 347-350 ◽  
pp. 1492-1496
Author(s):  
Yan Nan Zhai ◽  
Ling Gao ◽  
Yan Kun Tang ◽  
Jing Li ◽  
Shuang Luan
Keyword(s):  
Duty Cycle ◽  
Average Frequency ◽  
Voltage Source ◽  
Common Source ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Clock Signal ◽  
Clock Generation ◽  
Voltage Amplifier ◽  
Source Voltage

A clock generation circuit is proposed based on CMOSFET technology, which is comprised of a reference voltage source, a common source voltage amplifier, voltage controlled oscillator and timing circuit. By which a particular clock is produced, whose duty cycle is less than 50%. It is used 0.5 μ s CMOS process, HSPICE simulation results indicates that the average frequency of clock signal is 2.071MHz, and the average duty cycle is 31.565% .

scholarly journals Design and Analysis of Asynchronous Sampling Duty Cycle Corrector

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2594
Author(s):  
Gijin Park ◽  
Jaeduk Han ◽  
Woorham Bae
Keyword(s):  
Duty Cycle ◽  
Low Frequency ◽  
Operating Conditions ◽  
Cmos Process ◽  
Asynchronous Sampling ◽  
Operation Conditions ◽  
Correction Scheme ◽  
Control Scheme ◽  
And Performance ◽  
Settling Behavior

This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling behavior of an asynchronous sampling duty cycle corrector is limited in some operation conditions, which degrades its robustness and performance. This paper, therefore, performs analysis on the settling behavior of the asynchronous sampling in various operating conditions and proposes a control scheme to avoid the lagged settling. To verify the proposed duty cycle corrector and its analysis, a prototype design is implemented in a 40-nm CMOS process and its performance is verified by post-layout simulations. The proposed duty cycle corrector achieved very small duty cycle errors (less than 0.8%) and consumed 540 uW per one DCC unit.

High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms

2016 ◽  
Vol 25 (10) ◽  
pp. 1630006
Author(s):  
Sungkyung Park ◽  
Chester Sungchung Park
Keyword(s):  
Duty Cycle ◽  
High Speed ◽  
Logic Gate ◽  
Memory Systems ◽  
Data Converters ◽  
Frequency Divider ◽  
Cmos Process ◽  
Process Technology ◽  
Dynamic Memory ◽  
Frequency Dividers

Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.

scholarly journals A 6.89-MHz 143-nW MEMS Oscillator Based on a 118-dBΩ Tunable Gain and Duty-Cycle CMOS TIA

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2646
Author(s):  
Ahmed Kira ◽  
Mohannad Y. Elsayed ◽  
Karim Allidina ◽  
Vamsy P. Chodavarapu ◽  
Mourad N. El-Gamal
Keyword(s):  
Duty Cycle ◽  
Open Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Process Technology ◽  
Ultra Low Power ◽  
Mems Resonator ◽  
Mems Oscillator ◽  
Current Starving ◽  
Quality Factor Q

This article presents a 6.89 MHz MEMS oscillator based on an ultra-low-power, low-noise, tunable gain/duty-cycle transimpedance amplifier (TIA) and a bulk Lamé-mode MEMS resonator that has a quality factor (Q) of 3.24 × 106. Self-cascoding and current-starving techniques are used in the TIA design to minimize the power consumption and tune the duty-cycle of the output signal. The TIA was designed and fabricated in TSMC 65 nm CMOS process technology. Its open-loop performance has been measured separately. It achieves a tunable gain between 107.9 dBΩ and 118.1 dBΩ while dissipating only 143 nW from a 1 V supply. The duty-cycle of the output waveform can be tuned from 23.25% to 79.03%. The TIA has been interfaced and wire bonded in a series-resonant oscillator configuration with the MEMS resonator and mounted in a small cavity standard package. The closed-loop performance of the whole oscillator has been experimentally measured. It exhibits a phase noise of −128.1 dBc/Hz and −133.7 dBc/Hz at 1 kHz and 1 MHz offsets, respectively.

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