Design of CSD Coefficient FIR filters Using Diversified ACO

2021 ◽  
Author(s):  
Marika Morikawa ◽  
Kenji Suyama
Keyword(s):  
Fir Filters

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

Neural network for real-time synthesis of FIR filters

1989 ◽  
Vol 25 (17) ◽  
pp. 1199 ◽  
Author(s):  
G. Martinelli ◽  
R. Perfetti
Keyword(s):  
Neural Network ◽  
Real Time ◽  
Fir Filters

A novel technique for common sub-expression elimination for digital FIR filters using hit and miss transform

2021 ◽  
Vol 174 ◽  
pp. 107793
Author(s):  
A. Kumar ◽  
I. Sharma ◽  
S. Vishwakarma ◽  
L.K. Balyan
Keyword(s):  
Fir Filters ◽  
Novel Technique ◽  
Digital Fir Filters

A Clustering-Based Approach for Designing Low Complexity FIR Filters

2021 ◽  
pp. 1-1
Author(s):  
Mohammad Hussein Fawzi Nassralla ◽  
Naeem Akl ◽  
Zaher Dawy
Keyword(s):  
Low Complexity ◽  
Fir Filters

scholarly journals Design of Cut off-Frequency Fixing Filters by Error Compensation of MAXFLAT FIR Filters

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 553
Author(s):  
Daewon Chung ◽  
Woon Cho ◽  
Inyeob Jeong ◽  
Joonhyeon Jeon
Keyword(s):  
Closed Form ◽  
Error Compensation ◽  
Finite Impulse Response ◽  
Cutoff Frequency ◽  
Closed Form Solution ◽  
Form Solution ◽  
Fir Filters ◽  
Frequency Error ◽  
Computationally Efficient ◽  
Filter Type

Maximally-flat (MAXFLAT) finite impulse response (FIR) filters often face a problem of the cutoff-frequency error due to approximation of the desired frequency response by some closed-form solution. So far, there have been plenty of efforts to design such a filter with an arbitrarily specified cut off-frequency, but this filter type requires extensive computation and is not MAXFLAT anymore. Thus, a computationally efficient and effective design is needed for highly accurate filters with desired frequency characteristics. This paper describes a new method for designing cutoff-frequency-fixing FIR filters through the cutoff-frequency error compensation of MAXFLAT FIR filters. The proposed method provides a closed-form Chebyshev polynomial containing a cutoff-error compensation function, which can characterize the “cutoff-error-free” filters in terms of the degree of flatness for a given order of filter and cut off-frequency. This method also allows a computationally efficient and accurate formula to directly determine the degree of flatness, so that this filter type has a flat magnitude characteristic both in the passband and the stopband. The remarkable effectiveness of the proposed method in design efficiency and accuracy is clearly demonstrated through various examples, indicating that the cutoff-fixing filters exhibit amplitude distortion error of less than 10−14 and no cut off-frequency error. This new approach is shown to provide significant advantages over the previous works in design flexibility and accuracy.

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