Implement 32-bit RISC-V Architecture Processor using Verilog HDL

2021 ◽  
Author(s):  
Jin-Yang Lai ◽  
Chiung-An Chen ◽  
Shih-Lun Chen ◽  
Chun-Yu Su
Keyword(s):  
Verilog Hdl

scholarly journals Decision Tree-Based Adaptive Reconfigurable Cache Scheme

Algorithms ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 176
Author(s):  
Wei Zhu ◽  
Xiaoyang Zeng
Keyword(s):  
Decision Tree ◽  
Adaptive Algorithms ◽  
Memory Access ◽  
Access Time ◽  
Decision Tree Algorithm ◽  
Verilog Hdl ◽  
Tree Model ◽  
Cache Associativity ◽  
Cache Scheme ◽  
Reconfigurable Cache

Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms.

Design of PDF4172D Barcode Watermarking System Based on SOPC

2012 ◽  
Vol 220-223 ◽  
pp. 2903-2907
Author(s):  
Xiu Juan Zhang ◽  
Jia Ming Luan ◽  
Li Na Ni
Keyword(s):  
Digital Watermarking ◽  
Pci Bus ◽  
Verilog Hdl ◽  
C Language ◽  
Working Principle ◽  
Low Costs ◽  
Pci Bus Interface ◽  
Interface Chip ◽  
Sd Card ◽  
Hardware And Software System

This paper introduces the design of PDF417 two-dimensional barcode digital watermarking system with SOPC chip EP2C70F896C6 made by Alters fully. Analyzed structure and working principle of the hardware and software. System used video conversion chip VGA of DE2-70 development board made by Terasic Technologies and PCI bus interface chip SD card, realized the barcode watermark control with Verilog HDL and C language common programming. The system has many merits such as high velocity, good commonality and low costs etc.

scholarly journals Design of Power Efficient 32-Bit Processing Unit

2018 ◽  
Vol 7 (2.16) ◽  
pp. 52
Author(s):  
Dharmavaram Asha Devi ◽  
Chintala Sandeep ◽  
Sai Sugun L
Keyword(s):  
Low Power ◽  
System Design ◽  
Power Analysis ◽  
Low Power Design ◽  
Design Flow ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Front End ◽  
Verification Process

The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.  

scholarly journals A VLSI implementation of elevator control based on finite state machine using Verilog HDL

2018 ◽  
Vol 7 (2.8) ◽  
pp. 92
Author(s):  
Naresh Lagadapati ◽  
Manoj Karri ◽  
Tejaswini Vaddineni ◽  
Sk Mahaboob Subhani ◽  
K Hari Kishore
Keyword(s):  
Finite State Machine ◽  
Control Variable ◽  
Vlsi Implementation ◽  
Verilog Hdl ◽  
Control Module ◽  
Control Framework ◽  
Finite State ◽  
Control Procedures ◽  
High Utilization ◽  
Lift Control

In this cutting edge period, lifts have turned into a basic piece of any business or open complex. It encourages the quicker development of individuals and gear between floors. The lift control framework is a standout amongst the most critical perspectives in hardware control module that are utilized as a part of car application. Normally lifts are intended for a particular building considering the fundamental factors, for example, the tallness of the building, the quantity of individuals venturing out to each floor and the normal times of high utilization. The lift framework is composed with various control procedures. This usage depends on FPGA, which can be utilized for a working with any number of floors, with the predetermined sources of info and yields. This controller can be executed for a lift with the required number of floors by just changing a control variable in the HDL code. This approach depends on a calculation which decreases the measure of calculation required, by concentrating just on the pertinent guidelines that enhances the execution of the gathering of lift framework.

scholarly journals Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits

Computers ◽  
2022 ◽  
Vol 11 (1) ◽  
pp. 11
Author(s):  
Padmanabhan Balasubramanian ◽  
Raunaq Nayar ◽  
Okkar Min ◽  
Douglas L. Maskell
Keyword(s):  
Software Tool ◽  
Digital Signal ◽  
Automatic Generation ◽  
Arithmetic Circuits ◽  
Design Flow ◽  
Attractive Alternative ◽  
Design Environment ◽  
Verilog Hdl ◽  
Arithmetic Circuit ◽  
Practical Applications

Approximate arithmetic circuits are an attractive alternative to accurate arithmetic circuits because they have significantly reduced delay, area, and power, albeit at the cost of some loss in accuracy. By keeping errors due to approximate computation within acceptable limits, approximate arithmetic circuits can be used for various practical applications such as digital signal processing, digital filtering, low power graphics processing, neuromorphic computing, hardware realization of neural networks for artificial intelligence and machine learning etc. The degree of approximation that can be incorporated into an approximate arithmetic circuit tends to vary depending on the error resiliency of the target application. Given this, the manual coding of approximate arithmetic circuits corresponding to different degrees of approximation in a hardware description language (HDL) may be a cumbersome and a time-consuming process—more so when the circuit is big. Therefore, a software tool that can automatically generate approximate arithmetic circuits of any size corresponding to a desired accuracy would not only aid the design flow but also help to improve a designer’s productivity by speeding up the circuit/system development. In this context, this paper presents ‘Approximator’, which is a software tool developed to automatically generate approximate arithmetic circuits based on a user’s specification. Approximator can automatically generate Verilog HDL codes of approximate adders and multipliers of any size based on the novel approximate arithmetic circuit architectures proposed by us. The Verilog HDL codes output by Approximator can be used for synthesis in an FPGA or ASIC (standard cell based) design environment. Additionally, the tool can perform error and accuracy analyses of approximate arithmetic circuits. The salient features of the tool are illustrated through some example screenshots captured during different stages of the tool use. Approximator has been made open-access on GitHub for the benefit of the research community, and the tool documentation is provided for the user’s reference.

scholarly journals FPGA Implementation of Interrupt Controller (8259) by using Verilog HDL

2012 ◽  
Vol 48 (6) ◽  
pp. 12-19
Author(s):  
L. PadmaSree ◽  
Bekkam Satheesh ◽  
N. Dhanalakshmi
Keyword(s):  
Fpga Implementation ◽  
Verilog Hdl
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