Design of Power Efficient 32-Bit Processing Unit
2018 ◽
Vol 7
(2.16)
◽
pp. 52
Keyword(s):
The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit. The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.
2019 ◽
Vol 8
(2S7)
◽
pp. 472-477
Keyword(s):
Keyword(s):
Keyword(s):
2017 ◽
Vol 64
(6)
◽
pp. 1318-1327
◽
2018 ◽
Vol 7
(1)
◽
pp. 299-308
◽
Keyword(s):
Keyword(s):
1997 ◽
pp. 45-77
◽