scholarly journals Design of Power Efficient 32-Bit Processing Unit

2018 ◽  
Vol 7 (2.16) ◽  
pp. 52
Author(s):  
Dharmavaram Asha Devi ◽  
Chintala Sandeep ◽  
Sai Sugun L

The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.  

2005 ◽  
pp. 1-20
Author(s):  
Renu Mehra ◽  
Barry Pangrle

In present scenario world become completely digital. In digital devices the speed and life of the battery is the biggest issue .To resolve these problems there are my techniques for design the devices. A low power design technique is Gate Diffusion input (GDI). This review has the study of GDI technique which is most recent research in low power designing field. In this study many paper were reviewed. The review has structure of THE GDI cell, modeling and application. This review also presented the comparison of GDI technique with other technique of designing. The purpose of the study to find out most recent research in field of GDI. From this study we find out this technique mostly used for digital circuits. This review provides the current state of research and future scopes in this field.


Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.


2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.


2017 ◽  
Vol 64 (6) ◽  
pp. 1318-1327 ◽  
Author(s):  
Sheng-Yu Peng ◽  
Li-Han Liu ◽  
Pei-Ke Chang ◽  
Tzu-Yun Wang ◽  
Hao-Yu Li

2018 ◽  
Vol 7 (1) ◽  
pp. 299-308 ◽  
Author(s):  
Pierre Bellier ◽  
Philippe Laurent ◽  
Serguei Stoukatch ◽  
François Dupont ◽  
Laura Joris ◽  
...  

Abstract. In this work, we developed and characterised an autonomous micro-platform including several types of sensors, an advanced power management unit (PMU) and radio frequency (RF) transmission capabilities. Autonomy requires integration of an energy harvester, an energy storage device, a PMU, ultra-low-power components (including sensors) and optimized software. Our choice was to use commercial off-the-shelf components with low-power consumption, low cost and compactness as selection criteria. For the multi-purpose micro-platform, we choose to include the most common sensors (such as temperature, humidity, luminosity, acceleration, etc.) and to integrate them in one miniaturised autonomous device. A processing unit is embedded in the system. It allows for data acquisition from each sensor individually, simple data processing, and storing and/or wireless data transmission. Such a system can be used as stand-alone, with an internal storage in a non-volatile memory, or as a node in a wireless network, with bi-directional communication with a hub device where data can be analysed further. According to specific application requirements, system settings can be adjusted, such as the sampling rate, the resolution and the processing of the sensor data. Parallel to full autonomous functionality, the low-power design enables us to power the system by a small battery leading to a high degree of autonomy at a high sampling rate. Therefore, we also developed an alternative battery-powered version of the micro-platform that increases the range of applications. As such, the system is highly versatile and due to its reduced dimensions, it can be used nearly everywhere. Typical applications include the Internet of Things, Industry 4.0, home automation and building structural health monitoring.


Author(s):  
Thierry Taris ◽  
Hassen Kraimia ◽  
Amir Hossein Masnadi Shirazi ◽  
Shahriar Mirabbasi

Author(s):  
V. Gourisetty ◽  
H. Mahmoodi ◽  
V. Melikyan ◽  
E. Babayan ◽  
R. Goldman ◽  
...  

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