This paper proposed a single photon avalanche diodes (SPADs) designed with 0.18 [Formula: see text] standard CMOS process. One of the major challenges in CMOS SPADs is how to raise the low photon detection efficiency (PDE). In this paper, the device structure and process parameters of the CMOS SPAD are optimized so as to improve PDE properties which have been investigated in detail. The CMOS SPADs are designed in p+/n-well/deep n-well (DNW) structure with the p-sub and the p-well guard ring (GR). The simulation results show that with the p-well GR, the quantum efficiency (QE) is about 80% with the breakdown voltage of 12.7 V, the unit responsivity is as high as 0.38 A/W and the PDE of 51% and 53% is obtained when the excess bias is at 1 V and 2 V, respectively. The dark count rate (DCR) is 6.2 kHz when bias voltage is 14 V. With the p-sub GR, the breakdown voltage is 13 V, the unit responsivity is up to 0.26 A/W, the QE is 58%, the PDE is 33% and 37% at excess bias of 1 V and 2 V, respectively. The DCR is 3.4 kHz at reverse bias voltage of 14 V.
